Question Regarding the TCP/IP Stack Demo on XC-2

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Matt
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Question Regarding the TCP/IP Stack Demo on XC-2

Postby Matt » Sun Feb 14, 2010 1:33 am

Hi,

I have downloaded the TCP/IP Demo and have compiled it for a XC-2 and loaded it. I am getting the following messages from the debug "packet shorter than reported in IP header." and the program does not seem to be working correctly. Any ideas of what I may have done wrong.

I have set the enviroment variable TARGET to XC-2.

Anything else I should have done?

Thanks in Advance

Matt
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mike
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Postby mike » Mon Feb 15, 2010 11:02 am

Hi Matt,

Are you getting any other output when you run this? Also have you followed the instructions in the README e.g. Bonjour installation?

Mike
Matt
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Postby Matt » Tue Feb 16, 2010 11:47 am

Hi Mike,

Thanks for your reply. Im not sure what instructions you are talking about as the readme that I have with the TCP/IP stack 1.2 does not mention bonjour.

I can successfully compile and run the Full Firmware demo its just the lite demo that does not give me any joy.

Cheers

Matt
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mike
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Postby mike » Tue Feb 16, 2010 2:09 pm

I've just checked and there seem to be several READMEs in the download - the one you want is in /xmos_tcpip_1V2/src/xc2_firmware. This mentions Bonjour in the troubleshooting section.
Corin
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Postby Corin » Wed Feb 17, 2010 2:57 pm

Hi Matt,

I've had a look at the code and can reproduce your problem.

The issue is in the makefile for the demo. It is missing the -O3 optimization flag. This means that the MII code has timing problems as it cannot run quite fast enough.

So to fix it - in xmos_tcpip_1V2\build\demo\Makefile edit line 10 to read

XCC_FLAGS += -O3 -save-temps -g --show-report

rather than

XCC_FLAGS += -save-temps -g --show-report

We should be updating the code on the website soon to reflect this.

Kind Regards,
Corin
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Folknology
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Postby Folknology » Wed Feb 17, 2010 4:38 pm

That's interesting Colin^h^h^hrin

I have not yet had this experience on my XC-2, it all worked fine first time for me.

The nature of the problem however does conjure up some interesting questions. We are all probably familiar with the timing/latency issues around FPGAs and small variances between them. This however is a new type of error, where the compiler options can change the latencies in such a way that it may or may not work.

Colin^h^h^hrin - I'm intrigued did you run this through the simulator with different compiler settings to see if it be caught at that stage? Or could you only determine it on the hardware? The reason I ask is that if timings are close and the simulator can catch these issues it sounds like its worth doing a what-if multi-pass through the simulator with different compiler options. Also it would therefore be helpful to be able to automate a what-if-multi-pass simulator, does the simulator posses such a feature, if not could it be scripted externally via CLI perhaps?

regards
Al
Last edited by Folknology on Thu Feb 18, 2010 2:56 pm, edited 6 times in total.
DaveBest
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Postby DaveBest » Thu Feb 18, 2010 8:23 am

The need for full optimization for the mac/mii parts to truly work wasn't quite clear from all the readmes for allmost all ethernet stacks on XC.

One is quite baffled if even though demo code compiles fine you can't get ethernet to work until you tell the compiler to optimize.
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that_awesome_guy
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Postby that_awesome_guy » Thu Feb 18, 2010 2:00 pm

Folknology wrote:That's interesting Colin
Name fail... :lol: -

Corin wrote:Kind Regards,
Corin
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Folknology
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Postby Folknology » Thu Feb 18, 2010 2:57 pm

Apologies Colin sorry Corin :lol:

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