Integer clock cycle slip with AVB-DC + Mac Aggregate

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
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larry
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Re: Integer clock cycle slip with AVB-DC + Mac Aggregate

Postby larry » Mon Sep 05, 2016 7:04 pm

Could it be the Mac that's slipping? Do streams have identical timestamps before and after failure?
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akp
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Postby akp » Tue Sep 06, 2016 12:54 pm

I really don't know how to show that but if you give me an idea I can try it out. What I have found is that playback doesn't seem to be affected, just record.

It occurs when the frame clocks on two boards go out of sync and then resync. Usually the 48kHz clocks are phase locked. But sometimes they go out of lock and then relock. This is when the cycle slipping in record appears.
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larry
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Postby larry » Tue Sep 06, 2016 5:20 pm

If you can find a way to capture traffic outgoing from the Mac, then we can look for the point of failure and check that 1722 timestamps remain valid on both streams at the point of failure and that they are in sync with each other. A wire-tap such as the throwing star is perfect for this.

https://greatscottgadgets.com/throwingstar

It could be that the unlocking is how an endpoint reacts to a timestamp discontinuity after which everything is off by 1 (or more) for some reason.

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