XHRA-2HPA Reference Design Clock Issue

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
sfeine
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Joined: Wed Oct 12, 2016 3:05 pm

XHRA-2HPA Reference Design Clock Issue

Postby sfeine » Wed Oct 12, 2016 3:26 pm

Hi there,

I did a quick search to see if someone had already asked about this but I didn't see anything about it.

I have designed a DAC board based around the XHRA-2HPA reference design. I have gotten to the point that I am ready to program the QSPI flash and have stumbled onto a bit of a paradox.

I am using the Si Labs Si5351A clock generator chip (preprogrammed to output 24Mhz) and in reading through the chip's documentation I have realized that in the process of reprogramming the chip over I2C it turns off all of its output clocks (not just the ones being changed).
This means that when I ask the chip to change output frequencies for the audio clock outputs it will also stop outputting the system clock which will (theoretically) freeze the XMOS chip before the rest of the I2C config. data can be sent to the clock generator chip.

This seems like it would have been a problem in the creation of the reference design but in reading the documentation I haven't seen any notes about it.

Perhaps I am missing something but before I attempt to go any further with my design I would like to clear up this point of confusion.

Thank you for your help,
-Sam
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matthew1
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Posts: 48
Joined: Mon Oct 19, 2015 2:12 pm

Postby matthew1 » Thu Oct 13, 2016 9:44 am

Hi Sam,

it's not necessary to disable all of the clock outputs, but I don't think the Si5351 datasheet is very clear. Assuming you are using the Si5351A-B04486-GT and want to keep the CLK1 output running, you can write 0xFD to register 3, which will stop CLK0 and CLK2.

CLK1 comes from PLLB, so it's possible to change the configuration of PLLA if needed by whatever your required output frequencies are. However, I suspect you'll hit a problem if you need to reconfigure both PLL sources.

For example:

Code: Select all

int SI5351_ADDR = 0x62;
i2c_regop_res_t result;

// disable CLK0 and CLK2
result = i2c.write_reg(SI5351_ADDR, 0x03, 0xFD);
if (result != I2C_REGOP_SUCCESS) {
	printf("SI5351A: I2C write reg failed\n");
}

// ... you can set PLLA config and change
// ... CLK0 and CLK2 output parameters here

// soft reset PLLA (reg 177)
result = i2c.write_reg(SI5351_ADDR, 0xB1, 0x20);

// Wait a bit for Multisynth output to settle. 
delay_microseconds(1000);

// enable CLK0 and CLK2
result = i2c.write_reg(SI5351_ADDR, 0x03, 0xF8);
If you haven't already, take a look at this app note: https://www.silabs.com/Support%20Docume ... /AN619.pdf

The SiLabs clock builder tool is useful too.

Regards,

Matthew.
sfeine
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Posts: 2
Joined: Wed Oct 12, 2016 3:05 pm

Postby sfeine » Thu Oct 13, 2016 2:34 pm

Hey Mathew,

Thank you for your help.
I agree with you, the si labs data sheet does not make that clear at all.

I had designed my board under the assumption that any of the clock gen outputs could be used for any of my clocking signals. Therefore I did what I thought was intuitive and assigned the 24MHz system clock to output 0 on the si chip... looks like I need to revisit that design choice for the next revision.

Thank you again,
-Sam

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