Development board for XS1-L2

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
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RogerH
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Development board for XS1-L2

Postby RogerH » Tue Nov 09, 2010 11:35 am

Has anybody produced a development board for the XS1-L2 chips?

I want to develop some ideas around L2 and was hoping to avoid having to create a development board myself.

Thanks, Roger...
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Folknology
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Postby Folknology » Tue Nov 09, 2010 12:52 pm

Hi Roger

I have one in the pipe, but its number 2 on my list as I'm am in the process of doing my L1 board for Amino first.

regards
Al
ale500
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Postby ale500 » Tue Nov 09, 2010 1:01 pm

Hve you seen this already ?

http://www.xcore.com/projects/l2ulpi-2- ... gn-attempt

Eagle files exist.

It would be nice to know how to hand solder the L2.
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Folknology
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Postby Folknology » Tue Nov 09, 2010 1:21 pm

Hi ale500

Actually my L2 (Netstamp) board and Mika's L2 shared a common heritage, we were both working on the idea of a 2 layer L2 board. Currently my Netstamp board is on pause until I finish the Amino reference platform board first (too many projects!). I will then update the Netstamp design to meet the changes I have added to the Amino board as both need to run the Amino stack. I will get some updates out on the Amino project shortly in the Amino group as folks, quite rightly, keep jogging me about status.

But back to both Mika's and My L2 original designs the key point for us was to try and find a way to produce an L2 board using only 2 layers rather than 4. The reason is to significantly reduce the construction cost of such a reference board. Originally the L2 package choice was taken to enable such a 2 layer design to be possible. However one was never forth coming from Xmos, that's why Mika and I started our work in this area. The problem is escaping all of those double row QFN pins, it is very difficult!. In both of the current designs however we leverage the fact that adding Xmos recommended usb via the 3318 ULPI implementation renders many of the ports on the USB core useless. This of course means there are many fewer pins to break out in the first place. These un connected pins, provides a nice surface are to provide a ground plain and heat plain escape for the L2. Anyhow that's the principle idea behind the 2 designs, neither of which have been tested (to my knowledge ) yet.

Thus if you are taking on a L2 design you might want to take a look at some of our work, particularly if you are going for the elusive 2 layer design..

P.S. You would be better off using a hot plate or oven rather than a soldering iron for these puppies, although it might be possible with a rework station and lots of skillz ;-)

regards
Al
Last edited by Folknology on Wed Nov 10, 2010 9:05 pm, edited 1 time in total.
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RogerH
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Postby RogerH » Wed Nov 10, 2010 10:11 am

Hi Al,

Thanks for the information. You have given yourselves quite a challenge to get that done in 2 Layers.

I would be very keen to see both boards develop through to production. Especially your netstamp as that looks a great format.

I will follow both projects with much interest.

Regards, Roger...
nisma
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Postby nisma » Wed Nov 10, 2010 7:32 pm

I need to verify a combined layout, but it needs 20-35 days for the processing
becaus i´m on a remote DHL area and so i use standard registered airmail.
What do you want/need on it as support circuit ?.
I need four boards and want having two as spare, so 4 remain free.
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RogerH
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Postby RogerH » Thu Nov 11, 2010 11:08 am

Hi Nisma,

Can you please supply details of your board.

Thanks, Roger...
nisma
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Postby nisma » Fri Nov 12, 2010 5:25 pm

Primary, it´s just a design layout verification for a combined layout for xmos 1/2 core processor.
Apart from the Xmos cpu, spi flash, 4 leds (2 user led) and one button one PIC18F14K50 with 12Mhz
Xtal driving the Xmos clock is present. Additional things like ram, adc, usb tranceiver can be optionally
assembled, but probably don´t work (MT45V512KW16, ADS831, USB1T11). It´s unclear for me, if this interfaces really works at there normal speed or not in combination with the xmos cpu.
The standard 14 pin Jtag connector is used. If you want adding other things, let me know.
ale500
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Postby ale500 » Sat Nov 13, 2010 8:19 pm

External SRAM/SDRAM ? :)
nisma
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Postby nisma » Sun Nov 14, 2010 12:03 am

I have a Cellular Ram in the layout, MT45V512KW16. Probably it takes some time in order to
be useful, it´s not one of my primary todo items. Tell me what device including the pins constraints and
i try to include it.

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