How can I output a 4.8MHz clock from a 24MHz clock? Topic is solved

[xchips]

I'm using xk-216-mc multi-channel board, I'm trying to generate some specified I2S signals on this board:
Input MCLK = 24MHz.
Output BCLK = 4.8MHz.
Output LRCK = 48kHz.
i.e. OSR = 500 (i.e. 24MHz / 48kHz).
One channel = 50*BCLK.
I'm not sure if this requirement can be implemented. Now I only can get a set of I2S signals below:
Input MCLK = 24MHz.
Output BCLK = 2.4MHz.
Output LRCK = 48kHz.
i.e. OSR = 500 (i.e. 24MHz / 48kHz).
One channel = 25*BCLK.
The program below to get this set of I2S signals:

Code: Select all

on tile[0] : out buffered port:32 p_dout[2] = {XS1_PORT_1M, XS1_PORT_1N};
on tile[0] : in buffered port:32 p_din[2] = {XS1_PORT_1I, XS1_PORT_1J};
on tile[0] : port p_mclk = XS1_PORT_1F;
on tile[0] : out buffered port:32 p_bclk = XS1_PORT_1H;
on tile[0] : out buffered port:32 p_lrck = XS1_PORT_1G;
on tile[0] : port p_ctrl = XS1_PORT_8C;
on tile[0] : clock mclk = XS1_CLKBLK_2;
on tile[0] : clock bclk = XS1_CLKBLK_3;

{
    configure_clock_src(mclk, p_mclk);
    configure_clock_src_divide(bclk, p_mclk, 5);       // 24MHz / 10 = 2.4MHz
    configure_port_clock_output(p_bclk, bclk);
    configure_out_port_no_ready(p_lrck, bclk, 0);
    configure_out_port_no_ready(p_dout[0], bclk, 0);
    start_clock(mclk);
    start_clock(bclk);

    unsigned Lch_sample = 0xAC6B4D;
    unsigned Rch_sample = 0x1296479;
    while(1)
    {
        partout(p_lrck, 25, 0x01000000);
        partout(p_dout[0], 25, Lch_sample);

        partout(p_lrck, 25, 0x00FFFFFF);
        partout(p_dout[0], 25, Rch_sample);
    }

}

My questions are:
1. Am I doing the right things to output such I2S signals?
2. How can I output a 4.8MHz clock from a 24MHz clock?

Any idea will be appreciated!

[mon2]

Hi xchips. Just commenting on the clock generation and do not believe it is possible to hit your target value with precision using only software due to the limited divisor values. Recommending to save the grief and apply a sub-dollar PLL from SiLabs (Si5351A).

This is the 10 pin MSOP package.

http://www.xcore.com/forum/viewtopic.ph ... lit=Silabs

This PLL (when mated with a low cost 25 or 27 Mhz crystal - must be a crystal and not an oscillator), can output your 24 Mhz (with precision) and also your 4.8 Mhz (with precision). The component is I2C programmed but the factory (SiLabs) can pre-program the OTP inside the PLL to supply these 2 clocks upon power up. You can alter the clock value at anytime via I2C.

Download the free Clock Builder tool from the SiLabs website to get a feel for the precision of this device. We hit many target random clock values with 0 PPM for the 25 Mhz we wish to deploy. There is an $8 USD demoboard for this component from Adafruit (available through Digikey) but you will need to create the I2C bus master for programming. We used the StartKit (source code posted at the above URL) for this purpose.

http://www.digikey.com/product-search/e ... ?k=Si5351A

We are about to order this PLL part (tape & reel qty) with the 24 Mhz option as a power up default. On this note, you can then use any 2 single bit port pins on the XMOS device to create a simple I2C bus master to alter the PLL clock values.

For us, the single 24 Mhz clock output is suitable but can ask the factory if they can support 24 Mhz on CLK0 output and 4.8 Mhz on CLK1 output without a premium to the cost.



Hope this helps.

[xchips]

Thanks a lot for your response mon2, Using a PLL is a good idea. But I hope the I2S side can share the same 24MHz system clock. So it is impossible to generate some clock sets due to the limited divisor value.

Thanks a again.

[Ross]

It's not possible with a 24MHz clock. You could use an audio clock to run the xcore, if you are not using USB.

[xchips]

Thank you Ross, I've noticed that.