The SPI code produces a signal that looks like this
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__ ____
SEL \__________________/
____ _ _ ______
CLK \_/ \_/ ... \_/
The spec sheet for the device calls for the clk signal to be low when the SEL line goes low.
So, I modified the code so that the CLK starts and stop in a low state, but now my CLK line goes low as the data is clocked out of MOSI (which makes some sense, as it is tied to the clock block for MOSI). It looks like I need to delay the CLK signal by half-a-clock period. Is there a straightforward method for handling this?
Here's the relevant code:
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void spi_init()
{
// configure ports and clock blocks
configure_clock_rate(blk1, 100, SPI_CLOCK_DIV);
configure_out_port(spi_sclk, blk1, 0);
configure_clock_src(blk2, spi_sclk);
configure_out_port(spi_mosi, blk2, 0);
configure_in_port(spi_miso, blk2);
clearbuf(spi_mosi);
clearbuf(spi_sclk);
start_clock(blk1);
start_clock(blk2);
spi_sclk <: 0x00; // here's one of my changes
}
// read in response to previous byte, while issuing a new byte.
unsigned char spi_in_out_byte(unsigned char data)
{
// MSb-first bit order - SPI standard
unsigned x = bitrev(data) >> 24;
clearbuf(spi_miso);
spi_mosi <: x;
spi_sclk <: 0xaa;
spi_sclk <: 0xaa;
spi_sclk <: 0x0;
sync(spi_sclk);
spi_miso :> x;
return bitrev(x) >> 24;
}