New XMOS chips??!

[Folknology]

On the xCORE-200 eXplorerKIT port map the links look very different compared to current port maps, any chance of explaining those, are the Xmos links themselves different in nature?

I also notice there is no MSEL on the sys header for boot selection

regards
Al

[XMatt]

- The links are fully compatible with the XS1-L/U/A series of devices.
- MSEL is not needed on xCORE-200, JTAG boot mode is selected via an internal register in the top level JTAG TAP.

[Folknology]

Thanks Xmatt

Jtag boot feature is nice , a few less pins to worry about.. It's good to hear that the links are L1 backward compatible, looking at the port map they appear somewhat spread out compared to how they are on the L series, what I cannot see is the chip pinout, are they closely grouped from a pin point of view for each set A,D,E,H.

Does the boot actually use QSPI to improve performance as well as overlays?

Are there any architectural changes or improvements to the way ports operate, do they have the same 4ma/8ma drive capability?

I notice there are 3 VDDIO supplies VDDIOL,R and T, I am guessing the first 2 are Left and Right tiles but T is a new 2.5v requirement, what is this used for?

*Ok found the preliminary datasheet now can prob answer these already

regards
Al

[DavidW]

I'll post up a proper thread soon but in the meantime, please enjoy the disembodied head of Mark Lippett (XMOS COO) discussing the xcore-200 technology:

https://youtu.be/_0R5VS4SugU

[XMatt]

Thanks Xmatt

Does the boot actually use QSPI to improve performance as well as overlays?

Yes QSPI boot, the embedded flash parts have QSPI flash internally.

[infiniteimprobability]

new 2.5v requirement, what is this used for?

RGMII - Gig Ethernet!

[bearcat]

My likes:
External power again.
No 1.8V rail for the USB part.
TQ parts.

My concerns:
To use more than 2 tiles, must use 128+ pin parts. Rules me out. 128 pin part is too big.

I noticed the speeds as listed:

XL208Speed.PNG

So you can no longer get 125Mhz per core with only 4 active cores (500 MHz grade), as you can with the older parts?

Any details on the new instructions?

More options are better. Keep up the great designs...

[srinie]

So you can no longer get 125Mhz per core with only 4 active cores (500 MHz grade), as you can with the older parts?


Any details on the new instructions?

Yes, the maximum MIPS per core is 100

Please keep an eye on the documentation updates - they are to be made available soon.

[infiniteimprobability]

Yes, the maximum MIPS per core is 100

This is true (due to a 5 stage pipeline,up from 4) if you restrict the compiler/assembler to the XS1 instruction set.

Enabling dual issue allows 16b (short) instructions to be dual issued (this has to be explicitly done in the stream and mode change can be done at function call granularity). One lane can execute resource (I/O) or arithmetic and the other lane can do memory or arithmetic.

So at a maximum, you can chew through twice as many instructions making your 100MIPS actually 200MIPs. Of course getting to the 2x number is hard to achieve but expect 1.3-1.5x for optimised loops. The compiler is managing 1.2x average for general C code already. There will be a similar code size penalty, but with 4x the SRAM per tile and the ability to only compile certain files with dual issue, this can be mitigated.

There are a few other instructions which will boost speed too - especially load/store double (64b). This will really help on memcpy, dsp and push/pops.

As srinie says - more details coming shortly!

[Folknology]

On the new XE216-512-TQ128 chip is it possible to use USB or RMII on tile 1 and still be able to use XL3 link in 2 bit mode, likewise for XL4?