I is not a mater whether you are XMOS employee or not. I just know you are a XMOS lover and we can work together. But I should tell you that I am not experienced like you, I am a now comer.just to make some things clear. I am not an XMOS employee and therefore I also only got insight from the outside. Hence I cannot really answer the calculation that are done by XMOS in detail and offer my support just as a community member (even though I am interested in working together with you).
Please find the attached pdf and go through page 5.I do not know where this numbers come from. Sorry. But with your calculations in mind 8000 pixels make perfect sense. As you stated later you can have a number of LED buffers on different cores.
With single buffer we cam simply increase the pixel buffer size double. So we have to find out a better way of single buffer. We can declare a blanking flag and when the buffer will be written the flag will set and display scan routine will stop until the flag is reset. The flag will be reset at end of buffer write routine.A lot of the code works with double buffer and latching between those buffers. So it would be real hard to remove the second buffer (ok, if you just remove the latching it is easier). But you can expect to get some flickering problems due to parallel updates and readout. I think it is easier to try to use more buffers.
we can make another 6 more data pin with second connector of XC3. In core 1 we have 64KB buffer free. We have to declare a pixel buffer in core1, ethernet packet will be updated in this buffer through input channels and scan routine will fetch data from output channels of the buffer. Finally scan routine will use second connector of XC3 and send the core 1 buffer data to display module.This is no problem. On the XC3 there is a second GPIO port with a second connector which can be easily used for a larger address space.
Please comment on this point.
Do you mean that the ethernet chain of the prototype LED Tile project is not working at all. did you check with sending video file through PC and connecting two Tile in a chain??This was dead simple. The old network implementation was simply not working. Instead of debugging into the old and outdated network stack I wanted to integrate the official ethernet module from XMOS to benefit from future updates.
However integration of the official ethernet module is very good idea. But in that case we have to maintain the ethernet chain.
From hardware point of view BGA package is very difficult and expensive to use rather TQFP. Is it possible to port the system in a multiple 1 core board (att the core will be connected through sys channels). I am asking because PCB fabrication of TQFP package is feasible for me.I think this is a viable and good way. Eg. constructing something like the XC-3 but with more CPUs. Anyway I think that the XC-3 is a good hardware starting point since here you can test data throughput, memory usage per core and so on. A different hardware would either scale this up or break out the pins in a more convenient manner.
Thanks
Jags