STARTkit and external clock Topic is solved

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Post by mon2 »

Hi xchips. The Si5351A PLL is an amazing little device. I believe that you are correct on the use of the register 177. Please review the respective datasheet from SiLabs. Also realized only recently that XMOS has been using the same part on their XHRA device since 2015. So this gets even better for developers. The Si5351A can be ordered from the factory pre-programmed to power up and generate the desired clock values. For this task, you must use the CLOCK BUILDER s/w from SiLabs to create a custom P/N. However, you may not need to do this since XMOS already has such a version on the market (saw it on Digikey and Mouser).

Reference: p/n : Si5351A-B04486-GT

See here: ... 4486-GT%20

and ... dendum.pdf


So if practical for your project, consider to use this device with CLK1 to clock your XMOS device. This way, you should be able to leave PLL B untouched while configuring your custom clock on PLL A.

We can ping our local SiLabs FAE to confirm that the PLL A clock will remain active if working with only PLL B and vice-versa but believe our understanding is correct since the PLLs are independent of each other. In the past, have seen PLL vendors note the concept of glitch free transitioning from current clock to the new clock values but could not find such keywords in the Si531A documentation.

If you have the time, consider to source the very low cost Adafruit board (which is blank) and replace the PLL with the XMOS version to test these concepts.

The benefit of using the XMOS p/n is that you do not have to purchase any MOQ to receive programmed devices. For us, we have 24 Mhz on CLK0 so we will be sourcing in 1k pieces.
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Post by xchips »

Thank you very much, mon2. Your answers helped me a lot. I have a Si5351A EVB, and I did some tests just now. Then I got some answers from the tests:
1. Seems like CLK0 can have a chance to connect to PLLA or B by modifying register 16, bit MS0_SRC.
2. CLK0 (assume CLK0 is connected with PLLA) will remain active if:
register 03: do not change bit 0 (i.e. keep bit 0 = 0);
register 16: do not change a single bit;
register 177: do not reset PLLA.
But I don't know if there will be performance issue based on my settings?
3. To use 'ClockBuilder Desktop' to generate a register map and keep CLK0 unchanged, we must select the generation option 'Output clock assignment' from 'Automatic' to 'Manual'. But the app said this will cause some jitter issues if possible. (my desire clocks are: 8.192MHz, 12.288Mhz, 11.2896Mhz, 22.5792MHz, 24.576MHz, 45.1584MHz, 49.152MHz, 24MHz, 48MHz)

By the way, I think the correct method to remain CLK0 active is to keep these registers (or bit) unchanged:
1. register 03, bit 0;
2. register 15 (since NVM filed has changed its value);
3. register 16;
4. register 24, bit 0 and 1;
5. register 42~49;
6. register 165;
7. register 177, the PLL reset bit which CLK0 connect to.

Am I right on this device? If so, can we make these steps simpler?
Thanks again.