From what I see on my scope, pins are sampled on the falling and output on the rising edge.
I am trying to initiate a word transfer by sending a sync one clock cycle right before the word is being transmitted. Timing diagram attached. For transmitting, I am able to generate the desired timings. Output pins/ports are shortened with input pins/ports, and the inputs are driven by a clock block, that is output on one of the output ports.
Receiveing doesnt work tho, although I can see, that the values arent completely off. They just seem to be shifted, but im not sure why.
How I am trying to read the values is:
Code: Select all
while(1){
[[ordered]]
select{
case portInfsync when pinsneq(uiPinValue) :> uiPinValue:
/* frame sync just changed, did it transition to high? -> another 16 bit word is on its way!
* Continous clock! frame sync arrives one clock cycle BEFORE the first data bit.
* flush the buffer to put it in an empty/defined state - but only if we're not
* currently receiving */
if (uiPinValue){
if(!uiBytesExpected){
clearbuf(portInData);
}
uiBytesExpected += 2; // we expect two more bytes for each frame sync
}
break;
case uiBytesExpected => portInData :> uiData: // Read from buffer if more bytes are expected
// send to rx_processing thread for buffering
rxServerProcessing_c <: (unsigned char)uiData;
uiBytesExpected--; // reduce the expected remaining number of bytes
break;
} // select
} // while
What I expected this to do:
Data is being sampled on all ports on the rising edge.
This means, portInData has another bit being shifted in, while sync might (or might not) transition to high. For latter, the CPU spends some time checking, if we are transmitting transmitting already, and if not, the portInData buffer is flushed, throwing away all sampled bits including the bit that was just sampled. Because we got another sync signal, we expect 2 more bytes.
In the next sample cycle, our first data bit is sampled. In this case, the input port is buffered with 8 bits, so 7 cycles later, the first byte has been received.
Another 8 bits later, the second byte has finished sampling AND the next sync signal arrives. Here i wonder:
what happens?
Both events (port transition and port buffer full) fire at the same time, as both ports are sampled at the same time?
If this is the case, can I be sure that the higher priority case is always executed first?
Is my approach reasonable for what I am trying to achieve?