Multiple SPDIF receiver to I2S

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
Junior Member
Posts: 6
Joined: Mon Jan 08, 2018 4:14 pm

Multiple SPDIF receiver to I2S

Postby fabriceo » Sat Dec 22, 2018 9:40 am

Hi Guys,
Can someone help me to finalize my HW design by confirming feasibility of the following project ? also a first guidance on the application would be appreciated, just as a confirmation of feasibility and to sense the level of software headach to come :)

I m in the process of designing a multichannel dac board integrating XUF208 and I d like to manage 4 SPDIF receiver, as typically coming out of a player like OPPO-203 with Vanity 203 HD board. In this context the 4 SPDIF signals are synchronized together and generated from a single 44/48k or 88/96 master clock in the player.

The design includes a fractional PLL for generating a proper I2S synch clock, and the xmos will be configured as a single I2S slave channel in TDM8 mode.
the bit clock (11/12/22/24mhz) and the master clock (22/24mhz) are generated from the PLL. The TDM frame clock is generated by a logic divider.

here is a high level diagram of the configuration,
HLD multi spdif.png
(41.27 KiB) Not downloaded yet
HLD multi spdif.png
(41.27 KiB) Not downloaded yet

and the foreseen 1bit port mapping.
XUF208 pin map.png
(76.15 KiB) Not downloaded yet
XUF208 pin map.png
(76.15 KiB) Not downloaded yet

I have possibly a spare port (QSP_CLK / P1C0) that coud generate a reference clock for the PLL but I think it is not needed as the ClockGen.xc can calculate the value for the fractional PLL and send them over I2C right ?

Also I understood from other posts that the MCLOCK is not needed for the standard I2S_lib if we do not use XUD/USB right ?

I ve read many xmos application note and source code, including the famous AN00231_ASRC_SPDIF_TO_DAC. this all is inspiring but quite complex.

Many thanks for supporting our creativity!
User avatar
Active Member
Posts: 60
Joined: Thu Apr 04, 2013 10:14 pm

Postby Caleb » Thu Feb 07, 2019 11:29 pm

You didn't say what the PLL is so it's not clear what it requires. But I don't think you want to try to design something that dynamically adjusts the frequency of a clock synthesizer (jitter).

Understanding clockgen: It is used to generate the frequency reference for a CS2100 clock multiplier. It counts the number of samples it receives from the spdif rx thread and toggles an I/O pin every time it receives the number of samples that should be expected for 600 Hz toggle rate / 300Hz reference clock frequency. It knows how many samples to expect because it measures the rate of samples received. The CS2100's multiply ratio must then be changed to multiply by 81920 for 48kHz/96/192 or 75264 for 44.1,etc. The pin that is toggled for the frequency reference can be any I/O pin -and no need to "waste" a 1-bit clock synchronize-able pin. Various designs have used a pin of a 4-bit, port. You can change the way clockgen works to get better low frequency jitter performance from the CS2100. I never understood why 300Hz was used except that it's clever to find the largest integer common divisor of 44.1 and 48kHz. You could alternatively make the reference frequency 44.1 or 48kHz and leave the multiply ratio always set to 8. Anyway, there is a mechanism in clockgen - a fallback mode - that will use a timer to continue to make the 300Hz reference if the spdif rx has no signal.

I've used clockgen to gather samples from multiple spdif receivers - just using one of them used as the source for the frequency reference generation.

Who is online

Users browsing this forum: No registered users and 31 guests