TDM Master Xcore-200 using version 7.0.0

Discussions about USB Audio on XMOS devices
xmos_user123
Member++
Posts: 19
Joined: Tue Oct 01, 2024 1:43 am

Post by xmos_user123 »

Would the Wire up need to be done in Hardware ? or is there a way to internally send those clocks (Bit & LR) from one tile to another tile without incurring a Hardware change
User avatar
Ross
Verified
XCore Legend
Posts: 1119
Joined: Thu Dec 10, 2009 9:20 pm
Location: Bristol, UK

Post by Ross »

You’ll need to do this in HW.

xcore ports can only be clocked by another port on the same tile etc.
Technical Director @ XMOS. Opinions expressed are my own
xmos_user123
Member++
Posts: 19
Joined: Tue Oct 01, 2024 1:43 am

Post by xmos_user123 »

1) My understanding is that the clocks (Bit & LR) are outputs from XMOS so is it not possible at all to internally send it into the other tile or is there no other option than to physically tie those outputs currently on one tile to the other tile even though Bit clock and LR clock is generated internally?

2) If I happen to have the same Mclk on Tile 1 and Tile 0 is there something that can be done internally on the Xmos to generate the Bit & LR clocks from the Mclk on the tile that doesn't have the HW connection of the Bit and LR clock to enable the multi-tile I2S support?
User avatar
Ross
Verified
XCore Legend
Posts: 1119
Joined: Thu Dec 10, 2009 9:20 pm
Location: Bristol, UK

Post by Ross »

The general solution to add more data lines to an I2S (TDM) system where xcore is master is to add a slave on the other tile with external wires bridging the clocks. There isn't a way of doing this in the device.

on 2) reliably syncing up the start up condition would be the hard part, you might be able to do it with the careful use of port times and a synchronised (via channel) start up of the master clock. Not something I've attempted to be honest!
Technical Director @ XMOS. Opinions expressed are my own
xmos_user123
Member++
Posts: 19
Joined: Tue Oct 01, 2024 1:43 am

Post by xmos_user123 »

Noted. We'll take a look into it. On a slightly different note, I'm running into a situation where If I Fanout my 8channels of USB Audio to 4 different pins my LR clock stays at the expect rated of 48KHz but once I start fanning out to more than 4pins it LR CLK slows down. We tried fanning out to 5 pins and DOUT is sent to the 5th pin but the LR CLK starts to drop to ~46KHz instead locking at 48KHz. What are some ways I can resolve the issue of the LR clock changing when fanning out to more than 4 pins.
xmos_user123
Member++
Posts: 19
Joined: Tue Oct 01, 2024 1:43 am

Post by xmos_user123 »

Just following up on my previous question above ^… Any way to fix LR CLK changing ?
User avatar
Ross
Verified
XCore Legend
Posts: 1119
Joined: Thu Dec 10, 2009 9:20 pm
Location: Bristol, UK

Post by Ross »

This would be typical symptom of running out of "MIPS". Does a temporary increase in core clock freq solve the issue?
Technical Director @ XMOS. Opinions expressed are my own
xmos_user123
Member++
Posts: 19
Joined: Tue Oct 01, 2024 1:43 am

Post by xmos_user123 »

Currently running at a core clock of 500MHz. How much higher can I raise it up
User avatar
Ross
Verified
XCore Legend
Posts: 1119
Joined: Thu Dec 10, 2009 9:20 pm
Location: Bristol, UK

Post by Ross »

it's somewhat dependent on your design (you already mentioned a supply droop issue)

You should be able to bump it up to 6 or 700 to confirm the MIPS suspicion.
Technical Director @ XMOS. Opinions expressed are my own
xmos_user123
Member++
Posts: 19
Joined: Tue Oct 01, 2024 1:43 am

Post by xmos_user123 »

The supply issue has been sorted now but I'll raise it to 700MHz and see if that solves the issue. Also Just out of curiosity, does it matter how many pins I'm trying fanout to on a single tile ? (For example, If I had 5 pins on tile 0 and 3 pins on Tile 1 should it present an issue vs having 4 pins equally across tile 0 and tile 1 ? )