Par statement

[5ubject1ve]

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[mon2]

First, note that some of the terminology has changed on the website with respect to XMOS stdcore, threads, CPU, tile. Unfortunately some of older documentation is still referenced so proceed with caution.

Here is a good on-topic summary:

http://www.xcore.com/questions/2317/num ... gical-core

Specific to your question, here is my stab on the approach:

1) always start with the datasheet for your target CPU as there are many variations with more to follow. For the XMOS Explorer kit - assuming it is the Xcore-200 Explorer kit ?

This kit is based on the XE216-512-TQ128 device which means 16 logical cores with 512k ram and TQFP package of 128 pins. The "E" announces that there is internal Ethernet support (gigabit). Often USB 2.0 HS is also available on the same silicon and respectively the cost delta is very low to include vs exclude this feature.

Go here to download the respective datasheet:

http://www.xmos.com/support/silicon/dat ... t+%28XE%29

Specifically:
http://www.xmos.com/support/silicon/dat ... nent=18094

Always review the internal diagram and specs.

This datasheet reports:

16 real-time logical cores on 2 xCORE tiles

This means you have 2 CPU tiles and each CPU tile features 8 logical CPU cores.

While I have not verified the following (my usual disclaimer), the following should be correct:

within the

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par {}

[/b] statement, each such line (task) will be assigned to a separate logical CPU core with a maximum of 8 before that tile runs out of cores (on this specific component there are 8 cores per tile; some other parts may be only 4 or 6, etc.).

When you run out of logical CPU cores, apply the following prefix:

on tile[x]: .... // to force this task to run on tile[x] ie. on tile[0]

no harm to use:

on tile[0]: ... // for 1..8 tasks of your liking on your first CPU tile
on tile[1]: .. // for your next 1..8 tasks of your liking to run on the next CPU tile

for example:

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par {
on tile[0]: task1(5); // run this task in parallel on tile[0], next free logical CPU core
on tile[1]: task2(); // run this task in parallel on tile[1], next free logical CPU core
}

As you use more threads, the MIPS value will lower but to a deterministic value as noted in each datasheet. XMOS devices do not use interrupts as known on traditional CPU architectures.

Be sure to review that some of the GPIO port pins are bonded for use with a specific tile. There is a bit of a learning curve with this XMOS devices but the effort will be worth it in the end. XMOS is an excellent middle ground between traditional CPUs and FPGA devices. XMOS is different but in a good way.

References:
https://www.xmos.com/search/content?term=on+tile[0]

See the AN10036 from the above search. Also the XS1 port-to-pin mapping document.

Write back if you get stuck as there are some very seasoned pros on this website who will chime in to help. Also the staff of XMOS drops in often to assist.

Hope this helps.

[5ubject1ve]

.

[Bianco]

I want to add that you can also use the par statement within functions that is not the main function.
Because such a function is bound to a specific tile, you cannot use the on tile[] syntax and the number of threads you can start in parallel depends on the available number of free xcore's on that tile.