Possible for I2S bit clock ratio to be 48x Topic is solved

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audio
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Possible for I2S bit clock ratio to be 48x

Post by audio »

Hello,

The standard I2S in most instances today is to have a bit clock ratio of 64 x Fs or even 128 x Fs or higher.

I would like to now if it is possible to configure Xcore so that the I2S bit clock ratio is reduced to 48 x Fs.

Thank you!


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henk
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Post by henk »

Hi audio,

An XCORE should be able to do that (provided that MCLK isn't silly high). I am not sure the the standard I2S library can do it; you may need to hack it.

Can you specify an example MCLK frequency, LR clock frequency, and the number of bit clocks per LR-clock?

Eg, one standard I2S mode is a 24.576 MHz MCLK; a 48 KHz LR clock; and 64 clocks per LR clock. It would help to see some example values that you are after.

Cheers,
Henk
audio
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Post by audio »

Hi Henk,

Yes, I think that I2S mode with a 192KHz/24 bit signal will give a bit clock rate of: (64 x Fs) = (64 x 192,000) = 12.288 MHz

I wish to have the bit clock rate no more than 9MHz at 192KHz.

My thought was to use lower MCLK speeds than the standard 24.576 MHz & 22.5792MHz that I see most designs using.

I wish to lower the bit clock rate for all the following frequencies: 44.1KHz, 48KHz, 88.2KHz, 96KHz, 176.4KHz and 192KHz.

Can I just use lower frequency master clocks to get what I want?

Does XMOS support that?
henk
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Post by henk »

Hi,

For a 192 kHz sample rate; LRCLK = 192 KHz. Would you like a bit clock of 192*24*2 = 9.216 MHz, and a master clock of 18.432 MHz?

XCORE chips can do that, and you will need to modify the I2S library to achieve that.

For the 44.1 family you would need a 16.9344 MHz master clock.

Cheers,
Henk
audio
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Joined: Tue May 24, 2016 10:55 am

Post by audio »

Thank you Henk,

Thank you for you help!

I guess what I am trying to find out is what MCLK rates I would need so that when LRCLK = 192KHz the bit clock rate would be a maximum of 9MHz.

I am interested in a 24 bit word length for I2S (I do not want 32) so when you say "number of bit clocks per LR-clock" I am assuming that is to be 24.

I need to keep the bit clock rate below 9MHz for the highest frequency signal I will have, which for me is a 192KHz / 24 bit I2S signal.
henk
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Post by henk »

With an LRCLK of 192 kHz and 24 bits per sample, your bit clock will be just more than 9 MHz: it will be 9.216 MHz. To stay below 9 MHz you would need to limit yourself to 176.4 kHz, which at 24 bits per sample works out as a bit clock of 8.4672 MHz.

Do you have a codec that supports 48 bit clocks per LR-clock?
audio
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Post by audio »

Hi Henk,

It sounds like for what I want to do (limit bit clock to 9MHz max at 192KHz/24 bit) with XMOS I need to do some type of I2S hack.

I was wondering/hoping if it could be all be done within XMOS - sounds like it can not.

Thanks for your help!
henk
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Post by henk »

Hi audio,

I am not sure I understand why you say it cannot be done?

Yes, you will need to modify I2S. But, all hardware interfaces on XMOS chips are just software routines. So - making I2S run with 2x24 bits per LR-clock is just a software modification to the existing library.

As the I2S library is distributed in source format, you just need to add a dozen of lines or so to make it run at 2x24 bits rather than 2x32 bits.

Cheers,
Henk
audio
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Post by audio »

Hi Henk,

I hope it is clear that I know nothing about XMOS.

I need to spend some time educating myself.

I must have a interface that will accept a 24 bit depth and up to and including a 192 KHz sampling rate.

I would like to keep the bit clock frequency below 9MHz with a 192KHz / 24 bit signal.

You have said that the only way this is possible is if I limit my input sampling frequency to 176.4KHz maximum. Unfortunately I can not do that. I must have 192KHz functionality.

This is why I said I do not think it is possible to do what I want with XMOS alone.
henk
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Post by henk »

I see!

Ok - so it is the I2S standard that lets you down.

I2S has an LR-clock - which is the sample rate. 192 kHz in your case. It transmits stereo samples on each LR clock. You need 24 bits per sample, times two (for stereo) is 48 bits, times 192 kHz is 9.216 MHz.

Hence one cannot have 24 bits depth, 192 kHz and < 9 MHz bit clock - something has to give:

1) one can use fewer bits (at most 9000 / (2x192) = 23.4375 bits per sample)
2) one can use a lower sample rate (at most 9000 / (2x24) = 187.5 MHz)
3) one can allow a higher bit clock rate (at least 192 x 2 x 24 = 9.216 MHz)
4) use a different protocol for your audio (one that has more than 1 data wire)

Cheers,
Henk
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