SMI Interface Voltage

[DemoniacMilk]

"The SMI interface should be connected to two one-bit ports that are configured as
open-drain IOs, using external pull-ups to 2.5V. Ports 1C and 1D are notionally
allocated for this, but any GPIO can be used for this purpose."

For RX/TX pins, it is explicitly stated that you may use 3V3 instead, if the PHY is running 3V3 GPIOs.
I assume one may also use 3V3 on the SMI Interface without damaging the xcore?

[henk]

Hi,

I am not sure I understand the question. The pads for 1C/1D and RGMII are all powered from the same VDDIOT supply. This assumes that SMI and RGMII run at the same levels (both 2.5 or both 3.3).

Do you need different voltage levels on SMI and RGMII?

Cheers,
Henk

[DemoniacMilk]

just 3V3 on both SMI and RGMII.
I assumed 1C/1D were both powered from VDDIOT, but somehow did not find the info. Just wondered, as the SMI pin description talked about 2V5 only, while the RGMII pin description explicitely states 2V5 and 3V3.