USB Audio MC Clocking

[asibbald]

I'm trying to understand the clocking on this board ( because I'm trying to design a similar board with slightly different clocking ). I understand the way the Cirrus fractional-n clock generator is driven from the L2 chip with the SYNC_OUT signal. I can also see how the master clock generator frequency is changed in audio.xc depending on whether the sampling rate is a multiple of 48kHz or 44.1kHz, by passing the required master clock frequency to ClockingConfig():

/* Configure clocking for required master clock */
ClockingConfig(mClk);

When I follow this through, ClockingConfig() ( in clocking.xc ) then calls PllMult() to set the multiplier registers in the CS2300:

/* For L2 reference design configure external fractional-n clock multiplier for 300Hz -> mClkFreq */
PllMult(mClkFreq/300);

This implies that the L2 chip generates a 300Hz signal to the CS2300 ( on SYNC_OUT ). I cannot however see either WHY this is ( i.e. why the "magic number" of 300 ) or indeed WHERE it is generated.

Can anyone assist?

[Ross]

Hi there,

300Hz divides 44100 and 48000 :)

It is generated from the clockgen thread via a timer (this can also base this reference on a digital input stream such as ADAT/SPDIF)

[asibbald]

Indeed it does - so the cirrus doesn't need to do fractional-n! I hadn't realised that. Thanks for the clarification.

[namal]

Exactly, I agree with you
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