Reference Designs with 13MHz clock @ 500MHz PLL Settings

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
richard
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Post by richard »

bearcat wrote:Did any changes get made in V13 final regarding boot loading? I tried V13 beta1 without success, but not V13 final yet. I didn't notice any specific notes in the changes log.
Yes, xflash now computes how long the PLL will take to lock and uses this to determine the lengths of various delays in the boot process. This change went in between 13beta1 and the final release, so I'd recommend trying out the 13 tools.


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segher
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Post by segher »

Hey Bearcat, look! Good news for you!

Fingers crossed...
mmar
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Post by mmar »

Voltages seems good, is your oscilator 13MHz clock stable on time 1V start?
bearcat wrote:Power supply sequencing has been verified. The 1V rail starts 2mS after the 3.3V. You have to use two graphs to compare, but are included below.

The boot process actually blocks after the stage 1 loader has executed, so the tiles are actually running code.

Here's 1V vs 5V:
V5 5V vs 1V with 10K.JPG
Here's 3.3V vs 5V:
V5 5V vs 3.3V.JPG
bearcat
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Post by bearcat »

Thanks for the update Richard.

I will poke around a little more on the hardware side. I haven't looked at the oscillators in particular on this rev of the hardware.

Will take an hour or two to port up my latest code to V13 again. If in fact it now works (fingers crossed), I will then have to get the new XUD fully working from the older firmware code. Probably have to post a question or two on that if it's booting well.

Being able to use V13 is desired. Compiling on V11 is Slow (like 15 minutes).....

Thanks all.
bearcat
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Post by bearcat »

WOW!!! What a difference a new version of XTimeComposer makes.

My project now boots from V13 final (fingers crossed)!!! I still have to test over temperature, etc. So I can't say it's all great yet for sure....

Booting now takes significantly less time, probably 1/4-1/2 of the time it was before.

But I got the dreaded Stage 2 loader error when I enabled 8 or 10 tiles. With 10 tiles it was way over in memory. Bummer....

But I ran across a new setting in XFLASH. --s2l-partition-size? Didn't see that highlighted in the change log, or I missed it.

Sure enough, that solved the stage 2 loader issue!!!

My project is now booting all 10 tiles in V13.

Thank you all at XMOS. Great work.

Now on to figuring out the new XUD library....
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segher
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Post by segher »

Congratulations :-)
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Ross
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Post by Ross »

My understanding is the same as yours, for reduced jitter from the PLL you will want a low pre-divider.
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Ross
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Post by Ross »

By the way, did you know that you can set the following in the XN file?

PllFeedbackDivMin

PllDividerStageOneReg

PllMultiplierStageReg

PllDividerStageTwoReg

RefDiv

See here for more details: https://www.xmos.com/en/xn-specification?secure=1#node
bearcat
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Post by bearcat »

No, I wasn't aware that I could hard code the numbers in the XN file. That would assure the settings are as I want. Thanks for the tip.

I would like to take the reference design and test the audio THD+noise, and look at the harmonics, using the 2 different PPL settings. You would need to loop the reference output to another device's input for testing, with RMAA for example. 80dB down in the signal is more likely to show a difference. Be happy if anyone else is so inclined to test and post the results....
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Ross
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Post by Ross »

bearcat wrote:No, I wasn't aware that I could hard code the numbers in the XN file. That would assure the settings are as I want. Thanks for the tip.
No problem :)
bearcat wrote: I would like to take the reference design and test the audio THD+noise, and look at the harmonics, using the 2 different PPL settings
What audio interface(s) are you wanting to test (i2s/SPDIF etc)?
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