Hmm still not getting answer to some of these questions regarding the new U series, so I will add one more query:
Why are These multi-tile chips based around a 217 BGA rather than using say existing packaging like a 144 BGA used for G4s? 217 seems like an awful lot of balls given only 78 I/O pins, I expected these to be around the 140 ball mark. Is there some other great new feature for the multi-tile U series not mentioned that requires the extra connections like maybe external address pins?
regards
Al
New U series Chip confusion
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