Chained SliceKit Core Boards. Power-On Order Matters.

[TSC]

Hi

I have two SliceKit Core boards chained together. An XTAG-2 attached to a Core 1V2 as master, attached to a Core 1V1 as slave.

The problem was when I tried running a simple test program on the 4-tile setup, I'd usually get a debug error of "First stage multi-node boot failed".

After much head scratching, I found that powering on master before slave would allow a successful boot. Powering-on both at the same time or slave before master would always result in a boot failure.

Here is the XDE console output from a failed debug where the power-on sequence was wrong:

Code: Select all

.gdbinit: No such file or directory.
auto-solib-add on
Undefined command: "auto-solib-add".  Try "help".
connect --adapter-id Cqs8_Siv
0x00010000 in main ()
load
Loading section .text, size 0x222 lma 0x10000
Loading section .globcode, size 0x22 lma 0x10222
Loading section .cp.const4, size 0x4 lma 0x10244
Loading section .ctors, size 0x4 lma 0x10248
Loading section .dp.data, size 0x18 lma 0x1024c
Start address 0x10000, load size 612
Transfer rate: 4896 bits in <1 sec, 122 bytes/write.
Loading section .text, size 0x2ea lma 0x10000
Loading section .globcode, size 0x22 lma 0x102ea
Loading section .cp.const4, size 0x4 lma 0x1030c
Loading section .ctors, size 0x4 lma 0x10310
Loading section .dp.data, size 0x24 lma 0x10314
Start address 0x10000, load size 824
Transfer rate: 80 KB/sec, 164 bytes/write.
Loading section .text, size 0x2e6 lma 0x10000
Loading section .globcode, size 0x22 lma 0x102e6
Loading section .cp.const4, size 0x4 lma 0x10308
Loading section .ctors, size 0x4 lma 0x1030c
Loading section .dp.data, size 0x24 lma 0x10310
Start address 0x10000, load size 820
Transfer rate: 80 KB/sec, 164 bytes/write.
Loading section .text, size 0x24a lma 0x10000
Loading section .globcode, size 0x22 lma 0x1024a
Loading section .cp.const4, size 0x4 lma 0x1026c
Loading section .ctors, size 0x4 lma 0x10270
Loading section .dp.data, size 0x1c lma 0x10274
Start address 0x10000, load size 656
Transfer rate: 64 KB/sec, 131 bytes/write.
First stage multi-node boot failed, please check XN file and Xmos link connectivity

Here is the XDE console output from a successful debug where master was powered on before slave.

Code: Select all

.gdbinit: No such file or directory.
auto-solib-add on
Undefined command: "auto-solib-add".  Try "help".
connect --adapter-id Cqs8_Siv
0x00010000 in main ()
load
Loading section .text, size 0x222 lma 0x10000
Loading section .globcode, size 0x22 lma 0x10222
Loading section .cp.const4, size 0x4 lma 0x10244
Loading section .ctors, size 0x4 lma 0x10248
Loading section .dp.data, size 0x18 lma 0x1024c
Start address 0x10000, load size 612
Transfer rate: 4896 bits in <1 sec, 122 bytes/write.
Loading section .text, size 0x2ea lma 0x10000
Loading section .globcode, size 0x22 lma 0x102ea
Loading section .cp.const4, size 0x4 lma 0x1030c
Loading section .ctors, size 0x4 lma 0x10310
Loading section .dp.data, size 0x24 lma 0x10314
Start address 0x10000, load size 824
Transfer rate: 80 KB/sec, 164 bytes/write.
Loading section .text, size 0x2e6 lma 0x10000
Loading section .globcode, size 0x22 lma 0x102e6
Loading section .cp.const4, size 0x4 lma 0x10308
Loading section .ctors, size 0x4 lma 0x1030c
Loading section .dp.data, size 0x24 lma 0x10310
Start address 0x10000, load size 820
Transfer rate: 80 KB/sec, 164 bytes/write.
Loading section .text, size 0x24a lma 0x10000
Loading section .globcode, size 0x22 lma 0x1024a
Loading section .cp.const4, size 0x4 lma 0x1026c
Loading section .ctors, size 0x4 lma 0x10270
Loading section .dp.data, size 0x1c lma 0x10274
Start address 0x10000, load size 656
Transfer rate: 64 KB/sec, 131 bytes/write.
Loading section .text, size 0x4a6a lma 0x10000
Loading section .init, size 0x5c lma 0x14a6a
Loading section .fini, size 0x3a lma 0x14ac6
Loading section .text.__call_exitprocs_impl, size 0x2 lma 0x14b00
Loading section .rodata, size 0x4 lma 0x14b10
Loading section .eh_frame, size 0x44 lma 0x14b14
Loading section .cp.rodata, size 0x124 lma 0x14b60
Loading section .cp.const4, size 0x10 lma 0x14c84
Loading section .cp.rodata.cst4, size 0xac lma 0x14c94
Loading section .cp.string, size 0x15 lma 0x14d40
Loading section .dp.data, size 0x64 lma 0x14d60
Loading section .dp.rodata, size 0xf4 lma 0x14dd0
Start address 0x10000, load size 20119
Transfer rate: 108 KB/sec, 1676 bytes/write.
Loading section .text, size 0x4992 lma 0x10000
Loading section .init, size 0x5c lma 0x14992
Loading section .fini, size 0x3a lma 0x149ee
Loading section .text.__call_exitprocs_impl, size 0x2 lma 0x14a28
Loading section .rodata, size 0x4 lma 0x14a30
Loading section .eh_frame, size 0x44 lma 0x14a34
Loading section .cp.rodata, size 0x124 lma 0x14a80
Loading section .cp.const4, size 0x8 lma 0x14ba4
Loading section .cp.rodata.cst4, size 0xac lma 0x14bac
Loading section .cp.string, size 0x6 lma 0x14c58
Loading section .dp.data, size 0x38 lma 0x14c60
Loading section .dp.rodata, size 0xf4 lma 0x14ca0
Start address 0x10000, load size 19836
Transfer rate: 107 KB/sec, 1653 bytes/write.
Loading section .text, size 0x7b4 lma 0x10000
Loading section .init, size 0x5c lma 0x107b4
Loading section .fini, size 0x3a lma 0x10810
Loading section .text.__call_exitprocs_impl, size 0x2 lma 0x1084c
Loading section .rodata, size 0x4 lma 0x10850
Loading section .eh_frame, size 0x24 lma 0x10854
Loading section .cp.rodata, size 0x10 lma 0x10880
Loading section .cp.const4, size 0x8 lma 0x10890
Loading section .cp.rodata.cst4, size 0x4 lma 0x10898
Loading section .dp.data, size 0x30 lma 0x108a0
Start address 0x10000, load size 2240
Transfer rate: 109 KB/sec, 224 bytes/write.
Loading section .text, size 0x7b4 lma 0x10000
Loading section .init, size 0x5c lma 0x107b4
Loading section .fini, size 0x3a lma 0x10810
Loading section .text.__call_exitprocs_impl, size 0x2 lma 0x1084c
Loading section .rodata, size 0x4 lma 0x10850
Loading section .eh_frame, size 0x24 lma 0x10854
Loading section .cp.rodata, size 0x10 lma 0x10880
Loading section .cp.const4, size 0x8 lma 0x10890
Loading section .cp.rodata.cst4, size 0x4 lma 0x10898
Loading section .dp.data, size 0x30 lma 0x108a0
Start address 0x10000, load size 2240
Transfer rate: 72 KB/sec, 224 bytes/write.

I just thought I'd post this here because I spent two days trying to figure out what was causing the problem, and it might help someone else.

If anyone can think of an easy way of automating the correct power-on sequence, please let me know.

[Folknology]

Sounds like they should have a propagated Power Good signal or some such via the square slot to sequence this.

regards
Al

[segher]

Sounds like they should have a propagated Power Good signal or some such via the square slot to sequence this.

There is RST_N (on A16); PGOOD is only used to assert that, as far
as I can see. It should also be asserted by the debug adapter at
boot time. So it seems to me that something gets messed up that
a reset will not correct. Maybe there is ghost power flowing from
the slave to the master when only the slave is powered up? For example,
RST_N_IN on the slave has R11 to 3V3, which then goes via A16 on
the connector to RST_N_OUT on the master, where it goes to pins
1 and 13 on U18, which doesn't have its own 3V3 active yet. It's
hard to say, we don't even know _what_ is in a bad state / does not
work :-)