Hi - since you are using a custom audio interface, I can't answer that question for your code. For I2S as supplied in the ref design, it supports an MCLK:BLCK divider ratio of up to 8:1, so 24576000/8 = 3,072,000 bit clock. Divide by 64 (32b L+ 32b R) and you get 48000 exactly. So an MCLK of 24,576MHz is OK and not too high.which results in a MCLK of 24,576MHz. For 48kHz this is too high. It should be 12,288MHz. (Please correct me if I am wrong)
It really sounds like there is a rate mismatch somewhere. Can you either toggle an I/O in your ADAT routine or make an xscope call (https://www.xmos.com/download/public/Tr ... 9923A).pdf) to see in real time what is actually going on?