isn't sample rate supposed to change when locked to SPDIF?

[bowerymarc]

Do you mean

I don't get how it's actually changing the clock source.

?

In clockgen, the reference for the CS2100 is driven by port p. So whereever you see

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p <: pinVal;

or similar, it's sending an edge for the ref clock.

The code sending the edges is guarded by

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clkMode

or the timer comparing against timeNextEdge. If the clock is recovered, timeNextEdge is set far enough in the future that it doesn't fire

This is all controlled via endpoint zero which handles the USB audio control entities.

OK so the PLL is always being driven... but when you switch to internal clock rate, there's some hardware changes (PLL_SELECT, MCLK_FSEL) that happen, and I'm not seeing where those are called from EP0...

[infiniteimprobability]

PLL_SELECT, MCLK_FSEL are not modified in this build configuration. They are there to support fixed local oscillator mode, which is used when no digital input is supported. This makes cut down versions of the ref design simpler because all they need to do is select one of two MCLKs using MCLK_FSEL.