I read quite a lot of application notes on using Ports up to this point (yes, another topic on ports..).
But theres some questions that I still couldnt answer.
What i need is the following:
- 2+n bit wide, unidiretional bus with n data signals, frame sync and clock.
- The data signals are each transmitting bytes in parallel (not bits of a byte! Complete, serialized bytes)
- using lots of 1 bit ports
- using a 4/8/16 bit port (whatever is wide enough to fit, the bus width will be fixed)
Method 2) should not generate any timing problems and need less ports, but I think this approach requires to heavily modify the incoming data and mix bytes to generate the signal wanted? For two data signals id need to create a byte with clock info on bit 0 and 4, a data bit of byte1 on 1 and 5 etc and put that onto the port, what doesnt seem very nice to handle for different bus widths and would require quite some cpu time.
Do you have an idea/approach/hint on how to solve this?