I planned on using timestamped outputs on two 1-bit-ports to achieve an offset of one clock cycle between the two signals. The ports are clocked @ 8.3 MHz by the same clock block. Code as follows:
Code: Select all
// output the first data set
portOutfsync <: 0 @ uiTimestamp; // do a dummy byte output, get timestamp
portOutfsync @ uiTimestamp + 8 <: uiFSync; // .. and then output fsync and
portOutData @ uiTimestamp + 9 <: uiaZipped[0]; // .. data, data one clock cycle delayed
benchmarkTimer :> uiDurProc;
uiFSync ^= 0x1;
portOutfsync <: uiFSync; // this will block until the previous fsync has been transmitted
portOutData <: uiaZipped[1]; // this will block until the previous data has been transmitted
benchmarkTimer :> uiDurSent;
printf("send:%u us\n", (uiDurSent-uiDurProc)/100);
If i remove the first timestamp on the outputs:..
send:7864 us
send:7864 us
..
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portOutfsync <: 0 @ uiTimestamp; // do a dummy byte output, get timestamp
portOutfsync <: uiFSync; // .. removed timestamp
portOutData @ uiTimestamp + 9 <: uiaZipped[0]; // .. kept timestamp
Why does the timestamp add such a huge delay?..
send:0 us
send:0 us
..