output serialization for spi

[matrix]

Hi,

I would like to realize a simple spi interface by using 1 clock resource only.
Therefore clk, connected to an out port, should be the spi clock.

The problem is that serialization produces 1 unwanted extra clock cycle
at beginning of transmission, so 9 cycles are produced instead of 8.

Thanks for any solutions.

Code: Select all

# include <xs1.h>

out buffered port:8 outP = XS1_PORT_1A ;
out buffered port:1 outClock = XS1_PORT_1B ;
clock clk = XS1_CLKBLK_1 ;

int main ( void )
{
  configure_clock_rate (clk , 100 , 8);
  configure_out_port (outP , clk , 0);
  configure_port_clock_output ( outClock , clk );
 
  start_clock (clk );
  outP<:0xba;   //example data (MOSI)
  sync(outP);
  stop_clock(clk);
  while(1);
return 0;
}

[matrix]

Ok, so far my '1-clock-block' version of a spi-interface.

Very basic, fixed-mode spi and untested only, but simulator
wise it seems to be ok. :mrgreen:

Code: Select all

# include <xs1.h>

out buffered port:8 scl = XS1_PORT_1A ;
out buffered port:8 mosi = XS1_PORT_1B;
in buffered port:8 miso = XS1_PORT_1C;
clock clk = XS1_CLKBLK_1 ;


unsigned char spi_trans(unsigned char data);

unsigned char spi_trans(unsigned char outData)
{
 unsigned char b1;
 unsigned char b2;
 unsigned char inData;
 unsigned int expand=0;

 // double the bit-time of mosi data
 for(int i=0;i<8;i++) if((outData>>i)&1)expand|=3<<i*2;

 b1=expand>>8;
 b2=expand&0xff;
 start_clock(clk);
 mosi <:b1;
 mosi <:b2;
 //clock
 scl <: 0x55;
 scl <: 0x55;
 sync(scl);
 miso:>inData;
 return inData;
}


int main ( void )
 {
 unsigned char outData=0xba;
 unsigned char inData;

 configure_clock_rate (clk , 100 , 8);
 configure_out_port (scl , clk , 0);
 configure_out_port (mosi , clk , 0);
 configure_in_port (miso , clk);

 inData=spi_trans(outData);

 while(1);
 return 0;
}