UART input causing threads to not sychronise

[nuraven]

Hi there,

I have a problem trying to get outputs from two cores to sychronise. The outputs are 40kHz square waves. Everytime when I run the code for the first time, the outputs between the cores are synchronised. I then send an UART signal to the code to update the outputs, and everytime I send an update, the signals lag between 5 and 20 ms. At the moment, this happens even if there is no phase delays between each output (which is what I eventually will create).

What I would like is the outputs to be synchronised between cores. And also for there to be a continuous signal i.e. no lag between the previous outputs and the new outputs. It's fine to have a time delay before the new outputs start from when I send a UART update, but during this time delay the previous outputs must be continuously on.

The code for the main runs the 3 threads: core[0], core[1] and UART. The outputs are buffered.

I'm a bit lost as to what to do - so any suggestions would be helpful. Thanks!

Code: Select all

MAIN

par
	{
		#ifdef BOARD_ONE
		on stdcore[0]: output(clk0, portX0P8A, 0, clkInX0, clkOutX0, cAX0, cSync);
		on stdcore[1]: output(clk1, portX1P8A, 1, clkInX1, clkOutX1, cAX1, cSync);
		on stdcore[0]: uartManager(cAX0, cAX1);
		#endif
        }

Code: Select all

UART

while (1)
	{
		dataIn = (unsigned short)getByte();

		switch (dataIn)
		{

			case 254:
				par
				{
					cAX0 <: 0;
					cAX1 <: 0;
				}
				break;

			default:
				offset = 50* dataIn;

				 par
				 {
					 cAX0 <: offset;
					 cAX1 <: offset;

 				}
				 break;
 		}

	}

Code: Select all

OUTPUT

	switch (coreID) {
		case 0:
			configure_clock_rate(clk, 10, 5); // @ 10 MHz (T = 100ns)
			configure_port_clock_output(clkSyncOut, clk);
			break;
		case 1:
			configure_clock_src(clk, clkSyncIn); 
			configure_port_clock_output(clkSyncOut, clk);
			break;
	}

	// Load emission patterns
	switch (coreID) {
		case 0:
			getPatterns(patternsA);
	                break;

		case 1:
			getPatterns(patternsA);
			break;
	}

	configure_out_port(pA, clk, 0);								
	start_clock(clk);

        while (1)
	{
	select
		{
	    	case cInA :> offset:
	    		break ;

	    	default:

	            for (int i = 0; i < 50; ++i)
	               {
	                  currA = patternsA[i + offset];
	                  pA <: currA;
	               }
	            break;
	     }
	  }

[sethu_jangala]

Hi nuraven,

Could you attached your project workspace?

Sethu.

[nuraven]

Hiya,

Please find workspace attached.

Let me know if you have any questions.

Thanks.

[Folknology]

Although I haven't analysed the code, I might be tempted to run the the Output (Patterns) code on one core (tile) and the coms (UART) on another if it's possible with your ports/pins etc.

regards
Al

[sethu_jangala]

I had a quick look at the code and in the file output.xc, there is a loop in the default case of your select statement. If an event occurs on a channel during the time loop is executing, it waits until the loop finishes. So, is the lag between two signals. Try changing the default case as timer event and perform the output based on the timer event.

Hope this helps.

Sethu.