xCONNECT link network routing

[lilltroll]

I have played around with a design at block level that uses 3 UnA-128-FB217 chips.
The U series of chip has 4 internal and 5 external links, and I'm using that property to achieve 5 Links between the 2 on chip tiles to get 4 streaming channels + one (standard) channel.

• Is it possible to write a routing table for this design so it can be programmed in XC?

• Can all tiles boot from just one flash ?

XMOS Block 2.pdf

[sethu_jangala]

I think this topology is unsupported by the tools while using XS1-L devices. I did manage to build the system as shown below by changing the XN file:

Code: Select all

 
                             ================                                ===========

                             ||  L8 ------ L8   ||       -------------     ||  L8 ------ L8   ||           
                                                         -------------               
                             ================                                 ===========
                              L16             \  \                            /  /           L16
                                               \  \                          /  /
                                                \  \                        /  /
                                                   =======================

                                                        ||  L8 ------ L8   ||           

                                                    =======================
                                                             L16

I got the following error:
Error: XN11049 Network positioning failed (unsupported topology).

Attached the XN file I have tried. This might be possible by manually specifying the routing information in the XN file (not sure though).

[lilltroll]

Correct me if I'm wrong but, you need to write your own routing table when not using any standard topology :

https://www.xmos.com/support/xtools/doc ... y=platform configuration and xn&component=17556

The tool chain can only auto-generate the routing table for lines and hyper cubes (from 2D to 4D) including hyper cubes with lines attached.

Code: Select all

<RoutingTable>
  <Bits>
    <Bit number="0" direction="1"/>
  </Bits>
  <Links>
    <Link name="XLB" direction="1"/>
  </Links>
</RoutingTable>

[segher]

Looking at the center of your diagram, you have a triangle
of nodes. It is impossible to route this optimally; you'll have
to use at least one static forward to do this.

Routing direction on some node is decided by the top bit
that differs between the node's id and the target node id.
The top bit that is not equal on all three nodes can not be
different on all three; without loss of generality, we can say
the node ids are 00, 01, 1x. Node 1x will route messages
to both other nodes the same way.

[lilltroll]

If I connect one smaller SPI-EEPROM to each XMOS U2, can the current tool-chain flash the board with several external bootFlash?