My problem: Even though the transfers appear to work correctly, I get long waiting periods at the beginning and end of each transfer, and inbetween each transfer. After the chip select goes low, there appears to be a 32 cycle dead time (buffer clearing or something?), then my transfer, and then another slightly longer dead time, and then then chip select goes high. Then there is the inter-transfer delay. However, this period appears to be bottlenecked by something other than end_transaction, and sits at about 3.4us. Where are these delays coming from? Simulation waveforms attached (From top to bottom: CS, SCLK, MOSI, MISO).
Here is the code. The simulation is just outputing a 32bit test pattern for verification purposes. For the moment the control signals of the ADC aren't being simulated, it just outputs a 32bit word synchronous to the SCLK. Likewise, the MOSI transfer data are just a recognizable test pattern.
Code: Select all
void slave_simulation()
{
configure_clock_src(clk_1, p_clk_in_sim);
configure_out_port(p_data_1, clk_1,0);
configure_out_port(p_data_2, clk_1,0);
configure_in_port(p_trigger, clk_1);
start_clock(clk_1);
while(1)
{
p_data_1 <: 0x000AAAAA;
}
}
void app(client spi_master_async_if spi)
{
uint32_t outdata[1];
uint32_t indata[1];
uint32_t * movable buf_in = indata;
uint32_t * movable buf_out = outdata;
buf_out[0] = 0xcccccccc;
spi.begin_transaction(0, 25000, SPI_MODE_3);
spi.init_transfer_array_32(move(buf_in), move(buf_out), 1);
while(1){
select{
case spi.transfer_complete():
spi.retrieve_transfer_buffers_32(buf_in, buf_out);
spi.end_transaction(10);
spi.begin_transaction(0, 25000, SPI_MODE_0);
spi.init_transfer_array_32(move(buf_in), move(buf_out), 1);
break;
}
}
_exit(0);
}
int main()
{
spi_master_async_if i_spi[1];
par
{
on tile[0]: spi_master_async(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, clk0, clk1);
on tile[0]: slave_simulation();
on tile[0]: app(i_spi[0]);
}
return 0;
}
[1] http://www.ti.com/lit/ds/symlink/ads7263.pdf