32bits buffered ouput have 2ns delay.

[gzwpf]

my program:

configure_clock_src(clk_audio_mclk, p_mclk_in);
start_clock(clk_audio_mclk);
configure_out_port(p_i2so_bck, clk_audio_mclk, 0);
while(1)
{
p_i2so_bck <: 0xcccccccc;
}

input frequency of p_mclk_in is 22.5792Mhz
output frequency of p_i2so_bck should be 22.5792M/4 = 5.6448Mhz,
the period is 1/5.6448M = 177.15ns
my problem:
when i check the periods of output wave whith instrument, the periods is not constantly,it skips in two values 175.15ns and 177.17ns.
the DIFF whith two values is 2ns always while the output frequency changed!
why?how to solve ti? thanks.

[gzwpf]

2nsdiff.jpg

[larry]

All of the port logic is synchronous, running at the processor clock speed, typically 500MHz. An application clock signal is effectively resampled with 2ns resolution.

[infiniteimprobability]

ll of the port logic is synchronous, running at the processor clock speed, typically 500MHz

This is correct - for any externally clock that is not synchronous to the core clock, you will effectively get +-1ns jitter. The long term frequency difference will of course be 0ppm.

For most of the apps we see, for example I2S, the jitter does not matter as long as you meet the setup and hold times of the IC you are interfacing too. If you meet the setup/hold times by a little or a lot makes no difference to the sampled data.

There are some exceptions however, for example:
- The ESS DAC uses BCLK input to regenerate it's own MCLK using an internal PLL.
- SPDIF output. We do actually *just* meet the jitter spec but it's good practice to clean up the signal for downstream devices for maximum interoperability.

In these cases, adding a DFF clocked from your external application clock makes sense. Page 26 of the XU216 multichannel boards HW guide shows and example of this https://www.xmos.com/download/private/x ... 1.4%29.pdf

[gzwpf]

ll of the port logic is synchronous, running at the processor clock speed, typically 500MHz

This is correct - for any externally clock that is not synchronous to the core clock, you will effectively get +-1ns jitter. The long term frequency difference will of course be 0ppm.

For most of the apps we see, for example I2S, the jitter does not matter as long as you meet the setup and hold times of the IC you are interfacing too. If you meet the setup/hold times by a little or a lot makes no difference to the sampled data.

There are some exceptions however, for example:
- The ESS DAC uses BCLK input to regenerate it's own MCLK using an internal PLL.
- SPDIF output. We do actually *just* meet the jitter spec but it's good practice to clean up the signal for downstream devices for maximum interoperability.

In these cases, adding a DFF clocked from your external application clock makes sense. Page 26 of the XU216 multichannel boards HW guide shows and example of this https://www.xmos.com/download/private/x ... 1.4%29.pdf

thank you.