xCORE 200 MC Audio: TI DSP/TDM mode has inverted clock Topic is solved

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
User avatar
ccrome
Active Member
Posts: 60
Joined: Wed Sep 23, 2015 1:15 am

xCORE 200 MC Audio: TI DSP/TDM mode has inverted clock

Postby ccrome » Tue Apr 26, 2016 8:06 pm

Hi there,
On the TI Codecs (like TLV320AIC34), they can only manage TDM in their so-called DSP mode.

It does not do TDM in left-justified, right justified, or I2S modes, only in DSP mode.

The difference is that in DSP Mode, the bits are clocked out on the rising edge of BCLK, and sampled on the falling edge, whereas in the other modes the data is clocked out on the falling edge of BCLK and sampled on the rising edge.

How can I make data from the xCORE-200 part be sent on the falling edge of BCLK and sampled on the rising edge?

I think it will work if I put an inverter between XMOS.BCLK_OUT and CODEC.BCLK_IN.

Thanks,
-Caleb
Last edited by ccrome on Tue Apr 26, 2016 8:06 pm, edited 1 time in total.
View Solution
User avatar
Ross
XCore Expert
Posts: 768
Joined: Thu Dec 10, 2009 9:20 pm

Postby Ross » Tue Apr 26, 2016 9:23 pm

void set_port_sample_delay(void port p); applied to the data ports probably does what you want.
User avatar
ccrome
Active Member
Posts: 60
Joined: Wed Sep 23, 2015 1:15 am

Postby ccrome » Tue Apr 26, 2016 9:23 pm

Ross wrote:void set_port_sample_delay(void port p); applied to the data ports probably does what you want.
Thanks Ross. That seems to have done it.
-Caleb
User avatar
MAC
Member
Posts: 8
Joined: Wed Nov 19, 2014 4:12 am

Postby MAC » Fri Jun 24, 2016 2:37 am

Hi
I know this says the issue is solved, but I can't get it to work. Can i have more detail (not a software guy)

I think I have the same issue and need to have my mic data clock in on the falling edge of the SCLK. Tried to put:
set_port_sample_delay(PORT_I2S_ADC0); didn't work

Tried
set_port_sample_delay(p_i2s_adc); didn't work

and tried
set_port_sample_delay(p_bclk); and that didn't work

Not sure if i'm using it wrong or in the wrong place or what. Some complete syntax would be helpful

Thanks
User avatar
ccrome
Active Member
Posts: 60
Joined: Wed Sep 23, 2015 1:15 am

Postby ccrome » Fri Jun 24, 2016 2:37 am

MAC wrote:Hi
I know this says the issue is solved, but I can't get it to work. Can i have more detail (not a software guy)

I think I have the same issue and need to have my mic data clock in on the falling edge of the SCLK. Tried to put:
set_port_sample_delay(PORT_I2S_ADC0); didn't work

Tried
set_port_sample_delay(p_i2s_adc); didn't work

and tried
set_port_sample_delay(p_bclk); and that didn't work

Not sure if i'm using it wrong or in the wrong place or what. Some complete syntax would be helpful

Thanks
so, here's how I did it:

Code: Select all

From bbad6a78cf2677c15428e10ecb52e236f8ef1731 Mon Sep 17 00:00:00 2001
From: Caleb Crome <caleb@crome.org>
Date: Thu, 28 Apr 2016 09:18:02 -0700
Subject: [PATCH] Set clocking to be on the falling edge for the input ports. 
 This matches the DSP mode for the AIC3x.

---
 sc_usb_audio/module_usb_audio/ports/audioports.xc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/sc_usb_audio/module_usb_audio/ports/audioports.xc b/sc_usb_audio/module_usb_audio/ports/audioports.xc
index 308aa93..4ba3459 100644
--- a/sc_usb_audio/module_usb_audio/ports/audioports.xc
+++ b/sc_usb_audio/module_usb_audio/ports/audioports.xc
@@ -62,7 +62,12 @@ unsigned int divide, unsigned curSamFreq)
 #ifdef INVERT_BCLK
 #warning YOU HAVE THE BIT CLOCK INVERTED!
     set_port_inv(p_bclk);
-#endif
+#if (I2S_CHANS_ADC != 0)
+    for(int i = 0; i < I2S_WIRES_ADC; i++) {
+        set_port_sample_delay(p_i2s_adc[i]);
+    }
+#endif // i2s_chans_dac
+#endif // invert_bclk
 #else
     /* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
      * In this mode it outputs an edge clock on every tick of itsassociated clock_block.
-- 
2.7.4.1.g5468f9e
User avatar
MAC
Member
Posts: 8
Joined: Wed Nov 19, 2014 4:12 am

Postby MAC » Fri Jun 24, 2016 5:45 am

Thanks Caleb

I think i see my error... the index for the adc data port

I'll try it and let you know

MAC

Edit**********
Snip of code from audioports.xc that fixed the issue

Code: Select all

#if (I2S_CHANS_ADC != 0)
    /* Clock I2S input data ports from clock block */
    for(int i = 0; i < numPortsAdc; i++)
    {
        set_port_sample_delay(p_i2s_adc[i]);// ADDED VERY NECESSARY*************************
        configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
    }
#endif

Who is online

Users browsing this forum: No registered users and 0 guests