Development board for XS1-L2

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
nisma
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Re: Development board for XS1-L2

Postby nisma » Wed Nov 17, 2010 1:29 pm

Animated by this discussion, i´m close to have a full two layer breakout of the chip.
It passes metric DRC test, and need little work to pass imperial too (6mil/24mil and 0.15/0.6mm).
xmos_l2_full_breakout.jpg
Now the real question. What is the best footprint in order to make a dip component for prototyping.
As hint, on the west side there is 10 pin jtag interface (5xjtag+reset+debug+vccio+gnd) on the underside,
clock and reset are routed to NW corner.
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ale500
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Postby ale500 » Wed Nov 17, 2010 3:17 pm

Footprint ? all the IOs to pins :). It has 84 IOs, that means at least 2x50 :) so plenty of GND and +3V3.
If you space the two rows 0.9" (like DIP64) then it would be a big beast :) but if you do two rows on each side and you start to space them at 0.8" and 1" with 25 pins per row then... it will have some 2.6"x1.3" (64x32 mm) and will be great !

If you are making a breakout board then please include 1V regulator (several footprints), reset (several footprints), a crystal and a FLASH :).
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Last edited by ale500 on Wed Nov 17, 2010 3:59 pm, edited 1 time in total.
ale500
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Postby ale500 » Wed Nov 17, 2010 3:24 pm

If you use 2mm headers instead the thing could be smaller. I do not think it will be much cheaper, though and everyone will chime ! :mrgreen:
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lilltroll
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Postby lilltroll » Wed Nov 17, 2010 5:08 pm

nisma:
Hmm, Are you allowed to have a via on a pad when soldering with solderpaste ?
Probably not the most confused programmer anymore on the XCORE forum.
nisma
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Postby nisma » Wed Nov 17, 2010 6:07 pm

The pad/via on the north side are ok. On the south-east corner not really.
The point is, that some part of this line and vias including north-east corner line needs to be removed,
like the vcc signal located at south-west corner. Further, in the lib the vias and traces for m[0:3]
should be removed for having greater control of gnd/vcc routing in order to eventually bring gnd down on
the south-east corner. For now, the vias on the corners for vcc/gnd are only as placeholder, in order to
remaind the usage, there need to be removed. This image is a lib and not a layout image.
ale500
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Postby ale500 » Thu Nov 18, 2010 9:32 am

How are you planning to solder it ? If I may ask.
nisma
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Postby nisma » Thu Nov 18, 2010 1:47 pm

Soldering, Stencil and Reflow. If you mean Via/solder on the center Pad, i plan only to cover the non via part
with solder mask.

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