XS1-L1 SPI boot process?

[sjalloq]

Hey there,

can anyone describe the boot process - specifically the internal boot loader functionality. Does it just read 64K from SPI flash or is it more intelligent? I can't find the info in the L1 system spec.

Shareef.

[rao]

Have a look at "www.xmos.com/published/xsystem".

[trousers]

Assuming the boot mode pins are configured to boot from SPI, then on power up the boot ROM reads the first word from SPI which is used as the length of the boot image. The ROM then reads that many words into RAM then reads another word which is used as a CRC check. If the check succeeds then control is transferred to the start of RAM.

If you've written to SPI using xflash then this program is not your application. It's a boot loader which configures the machine (clock dividers, xlinks (if used), and so forth) then has a poke around in the SPI looking for bootable images.

There will always be at least one bootable image located right after the boot loader. This is termed the factory image. There may follow any number of additional images. Each image has a version tag associated with it. One of the bootable images is chosen based on its version tag. In the 9.9.2 tools the numerically highest tag is picked. In the next release this behavior can be over-ridden.

[sjalloq]

@rao - thanks, but that's the document I referenced above.

@pants - that's what I wanted to know, thanks. Now were did you find that information in their documentation? Or is it not?

Thanks a lot.

[Folknology]

What frequency does the SPI clock run at boot?

[trousers]

The boot ROM's behavior is described here http://www.xmos.com/published/xsysteml (that's a funny URL; it ends up pointing to a pdf). The interesting bit is section 2, "Booting the XS1-L".

The xflash loader behavior is described (briefly) here http://www.xmos.com/published/xtools_en in appendix G called "The libflash library".

[trousers]

What frequency does the SPI clock run at boot?

The boot ROM runs it very slowly. Really, really, slowly. Xflash's boot loader bumps it up to 25Mhz.

[Folknology]

I am exploring the design of L1s to be able to boot from each other in a chain by using Links C & D. This way I hope to be able to boot them from a single flash (the one 1st in the chain from the xtag2) using mode:

10 boot from ChanEnd 0, enabling LLinks C-H.

I was going to use a circuit design similar to the XK1 boards by also daisy chaining the JTAG/XTAG.

I would like to check that:

1) This is possible given the proposed chaining architecture for L1s
2) That one could use both L1s and L2s in the chain.

Are there and hardware/software gotchas that I need to be aware of when doing this.

I would also like to use the same Links as communication channels post boat, I am assuming that this is also ok.

regards
Al

[trousers]

I would like to check that:
1) This is possible given the proposed chaining architecture for L1s

Yes, it is.

2) That one could use both L1s and L2s in the chain.

Probably. Which means that I don't see why not but it hasn't actually been tried AFAIK.

Are there and hardware/software gotchas that I need to be aware of when doing this.

A couple:
- You need to put pull-down resistors on the receive lines of any xlinks that are enabled but not connected, else they can receive phamtom garbage.
- Your XN file will be a thing to behold.

I would also like to use the same Links as communication channels post boat, I am assuming that this is also ok.

Yes.

[Folknology]

Thanks Awesome

I notice on the XK1 that Xmos daisy chain through in from Link C and out to next XK1 via D.

If I swapped these around in my design (in D out C), would that cause a nightmare or just be a simple change in the xn file?

P.S. I am assuming the use of Xtag2 to program them similar to how the XK1 operates.

regards
Al