One Bit Sigma Delta DAC

[Andy]

I've been concentrating on trying to produce a PA solution rather than a DAC that needs a PA, so I've not really spent much time on that. I have had a single 1 bit port driving an RC filter for testing. From my experience I wouldn't expect much better performance than that which I've posted though. Are you going to drive a speaker or is it basically a DAC solution you're after?

I'm interested in XMOS -> powered speaker at the moment, however the ClassD amp does sound interesting!

Did the 1 bit PWM + RC filter you tested use the upsample/filter method you posted and if so was the quality any better than a standard PWM?

[Woody]

Simple answer: yes!

So you're basically trying to implement a DAC and you will have an external power amp to drive your speaker. The 1 bit PWM + RC solution I implemented interpolated the samples (upsampled and filtered them). The results are significantly better than using standard PWM on the 48kHz samples. Of course the downside is that you use a thread to perform this interpolation.

So tweaks I used to improve the performance are:

• interpolating the samples from 48kHz to 384kHz

• increasing the reference clock frequency to max to get best PWM resolution

• maintaining fractional error from one (interpolated) sample to the next

• centralising the PWM pulse within the PWM sample duration

[Andy]

So tweaks I used to improve the performance are:

• interpolating the samples from 48kHz to 384kHz

• increasing the reference clock frequency to max to get best PWM resolution

• maintaining fractional error from one (interpolated) sample to the next

• centralising the PWM pulse within the PWM sample duration

I understand all these apart from the last - is this as opposed to edge aligned PWM?

[lilltroll]

I recorded the output voltage 8bit@1Gs/s on the small speaker on the XC-1 card playing a sin at 50% of maximum amplitude. Thereafter I plotted a histogram over the voltage distribution of the recorded samples.

In a ideal situation we would only se 0 V and 5 V

PWM.png

Also a plot over 10us of time below. (The Y-asix resolution is enhanced by LP filtering at 100 MHz)

PWMxt.png

If you recalculate this deviation to dBs of distortion - it means a lot of distortion.

I will check how it looks like on another output pin not driving the speaker (Have not checked the schematics yet).


(A class D-amplifier (most often) uses a LP-filtered analog feedback loop that compensates for the error in Y-led in the rail and the nonperfect transitoroutput by chaning the switchtiming in the X-led.)

[Woody]

centralising the PWM pulse within the PWM sample duration

I did some experimentation with single sided and double sided PWM schemes. Double sided gave much better distortion, but single sided gave much better noise. I thought that the advantage that double sided gave to the distortion, was perhaps because the centre of it's pulse kept basically in the same place. So I tried it doing this with single sided PWM and was able to get the best of both worlds.

Here's an explanation with waveforms.
If you look at the +ve pulses, for a -ve sample the centre of the +ve pulse is near the start of the cycle, for a zero sample it's a 1/4 of the way through the cycle, and for a +ve sample, the centre of the +ve pulse moves out past 1/4 of the way through the cycle.

Code: Select all

_/---\_______/---\_______/---\_______/---\_______/---\_____ Single sided PWM -ve sample
_/-----\_____/-----\_____/-----\_____/-----\_____/-----\___ Single sided PWM zero sample 
_/-------\___/-------\___/-------\___/-------\___/-------\_ Single sided PWM +ve sample 

So I thought I'd try to keep the centre of the +ve pulse at the centre of the PWM cycle. This means changing the turn on and off time of the PWM depending on the sample value.

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__/---\_______/---\_______/---\_______/---\_______/---\____ Single sided PWM (centred) -ve sample
_/-----\_____/-----\_____/-----\_____/-----\_____/-----\___ Single sided PWM (centred) zero sample 
/-------\___/-------\___/-------\___/-------\___/-------\__ Single sided PWM (centred) +ve sample

And I got much better results!

[Berni]

There should not be any difference between the two as they are identical signals. 2nd one you drew is just phase shifted a bit and you cant have phase shift in a single pwm signal.

PWM can sound very good with high frequency. D-Class amplifiers basically send a PWM signal in to a LC filter to smooth it in to a analog signal, but they normally use a few 100KHz to a few MHz as the PWM frequency and have a feedback loop to keep the output under control. These amps can provide very low distortion and are really efficient.

But for getting top quality audio out of a xmos chip i really don't recommend it. But if you just want to quickly get audio out its great, also for voice and such applications it can be more than good enough. Main limitation of the pwm method is only 8bits of depth, and the timing of the samples arriving at the output may quickly go off by a bit and create distortion.

[Woody]

Berni, you're right that the centred PWM signals displayed are just time shifted versions of the uncentred ones, that won't have any different effect as I showed it. This is true when the samples are the same from sample to sample, but not when the samples change. I've compared the following samples: 0x0000, 0x4000, 0x0000, -0x4000 in both schemes indicating the centres of each pulses below. This should help clarify where the benefits occur.

Code: Select all

_/-----\_____/-----\_____/-----\_____/-----\_____/- zero samples for timing reference
.*12^        *12^        *12^        *12^           centres occur regularly

_/-----\_____/---\_______/-----\_____/-------\___/- samples: 0, -0x4, 0, +0x4 normal PWM. Pulses start at the start of PWM cycle.
.*12^        *1^         *12^        *123^          centre of +ve phase changes with sample value

_/-----\______/---\______/-----\____/-------\____/- samples: 0, -0x4, 0, +0x4 centred PWM. Pulses centred around centre of PWM cycle.
.*12^        *12^        *12^        *12^           centre of +ve phase constant

[Woody]

The app note giving an overview of how a class D power amp can be implemented on an XCore has been published here:
http://www.xmos.com/published/classdan

Enjoy it :)

I will publish the code too soon.

[lilltroll]

If the real implementation is done as showed in the pdf, then you moved the SNR problem to the rail instead.
If it's a feedforward solution: If the rail is noisy, the output will be noisy as well.

Is it really cheaper in $ to put such a effort in a stable rail to generate a 90 dB SNR output when looking at the total cost of a consumer system?
In a product I guess that the power supply will either be a LiPo battery or something that starts with 2 pins in the vall @ 230V/110V. A smaller power adapter with a very simple voltage regulation cost under 2$ in mass production (excluding the plastic around it). If you use the LiPo without expensive supercaps - the output resistance of the battery is to large to handle a 4 ohm load without a larger voltagedrop on the rail - generating even tones of distortion to the output, modulated by the |current| drawn from the battery. :!: :?:

[Berni]

Well i still don't see anything special in that waveform, that is normal PWM. Its fixed frequency and varying duty. An PWM preperial on a MCU will spit out such a waveform.

Altho there is one thing that can help pwm. dsPICs have a so called glitch free PWM. It means that when you give it a new value it gets writen in to the register on the next PWM cycle to prevent he PWM doing something screwy(make a glitch) when its value changes in the middle of the PWM period.

I haven't done this glitch free pwm on a xmos so it could be reason i had much more noise than the dsPIC.(Its also hard to get instruction cycle perfect timing on software pwm)

As for the appnote, the inductors are needed for a proper D class. This circuit can be used with BD type modulation and will not provide the high efficiency. Also its limited to only very little powers as going higher will fry the speaker (thermally) with the high frequency components.