DSD/DOP in audio Reference Design

[AudioBoy]

Hello,

I have some questions about DSD.

1) In Audio Reference Design Native DSD and DoP are implemented, but not for L1 application.
This is a CPU limitation?

2) What the difference between "Native DSD" and DoP? As I remember, it is always used DoP technology for USB Audio Class II.

3) It was not clear for in DoP description about 05/FA markers. As I understood, transmission is 3 byte, where high byte is marker and 2 lower bytes are DSD stream, and all this in 176K PCM stream.
PCM stream consists of 2 channels, that are transmitting sequentially - Left-Right,Left-Right,...
One 2 channel sample is 2x3byte, 3 byte for left and 3 bytes for right.
With DoP, high byte in each channel should be the marker, but I have not found which marker correspond to which channel?
Because at PCM (I2S) left channel is always first, can I suppose that it is transmitted with 0x05 marker and the right channel - with 0xFA? And the sequence looks like:
...-0x05-16bit_left-0xFA-16bit_right-0x05-16bit_left-0xFA-16bit_right-...

or for I2S:
LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0xFA, 16 bit right stream

?

Thank you.

[AlexAdvice]

Maybe I'm wrong, but as I remember, this is not correct:

LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0xFA, 16 bit right stream

One LRCLK period has the one marker, next LRCLK period - another:
...
LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0x05, 16 bit right stream
LRCLK=1; SDATA = 0xFA, 16 bit left stream
LRCLK=0; SDATA = 0xFA, 16 bit right stream
LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0x05, 16 bit right stream
...

[Ross]

Hello,

I have some questions about DSD.

1) In Audio Reference Design Native DSD and DoP are implemented, but not for L1 application.
This is a CPU limitation?

No restriction, you can use on L-series devices.

2) What the difference between "Native DSD" and DoP? As I remember, it is always used DoP technology for USB Audio Class II.

DoP is complant to the open DoP spec (http://dsd-guide.com/dop-open-standard). The player must add headers to the audio stream to indicate DSD data. Driver support is therefore not required.

"Native DSD" is termed to mean the proprietary XMOS support for DSD via ASIO with driver support.

3) It was not clear for in DoP description about 05/FA markers. As I understood, transmission is 3 byte, where high byte is marker and 2 lower bytes are DSD stream, and all this in 176K PCM stream.
PCM stream consists of 2 channels, that are transmitting sequentially - Left-Right,Left-Right,...
One 2 channel sample is 2x3byte, 3 byte for left and 3 bytes for right.
With DoP, high byte in each channel should be the marker, but I have not found which marker correspond to which channel?
Because at PCM (I2S) left channel is always first, can I suppose that it is transmitted with 0x05 marker and the right channel - with 0xFA? And the sequence looks like:
...-0x05-16bit_left-0xFA-16bit_right-0x05-16bit_left-0xFA-16bit_right-...

or for I2S:
LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0xFA, 16 bit right stream

?

Thank you.

No, incorrect. The marker is the same for all channels in that block: More like:

DATA = 0x05, 16 bit left stream
DATA = 0x05, 16 bit right stream
DATA = 0xFA, 16 bit left stream
DATA = 0xFA, 16 bit right stream

There is no LRClk in DSD...

[Ross]

Maybe I'm wrong, but as I remember, this is not correct:

LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0xFA, 16 bit right stream

One LRCLK period has the one marker, next LRCLK period - another:
...
LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0x05, 16 bit right stream
LRCLK=1; SDATA = 0xFA, 16 bit left stream
LRCLK=0; SDATA = 0xFA, 16 bit right stream
LRCLK=1; SDATA = 0x05, 16 bit left stream
LRCLK=0; SDATA = 0x05, 16 bit right stream
...

Yes this is more like it, though there is no LRCLK. The physical implementation of stereo DSD is two data-lines (one left, one right) and one clock line.

[AlexAdvice]

Yes this is more like it, though there is no LRCLK. The physical implementation of stereo DSD is two data-lines (one left, one right) and one clock line.

Yes, I know.
But I think Audioboy describe DoP in terms of PCM, like I2S-bus.

[Ross]

Sorry, thought the two posts were from the same person for some reason!