I ported a succesfully tested project on a board with a XS1-L8A-64-LQ64A processor.
I developed the first firmware version using a startKit.
In my application I have a slave SPI section and the FSM that manages it has the following code:
while(1){
select{
//Wait for select line to change
case p_spi.ss when pinsneq(ss_val) :> ss_val:
//Check to see if the change to the port means SPI_SS is high or low (selected)
if (ss_val & SS_BITMASK) {//SS is high - de-selected
spi_state = SPI_IDLE; //Return to idle if SS is high (de-asserted)
// printstrln("SS gone high");
}
else{ //SS is low, active
if (spi_state == SPI_IDLE){ //check to see if start of SPI cycle. If so..
clearbuf(p_spi.miso); //clear port buffers in case of previous partial transfer
clearbuf(p_spi.mosi);
buff_index = 0; //start the buffer at zero
out_data_rev = bitrev(spi_miso_buffer[mng_miso_index]) >> 24; //Calculate first byte to send for next state
p_spi.miso <: out_data_rev; //Put first word into Tx port buffer before first SPI clock edge
spi_state = SPI_SELECTED; //change to next state
// printstrln("SS gone low");
}
}
break;
//If SCLK goes low following SS, then it's definitely the start of SPI transaction
case (spi_state == SPI_SELECTED) => p_spi.sclk when pinseq(0) :> void:
if (!data_transferred) missed_transfer = 1;//Flag that client missed a SPI transfer
data_transferred = 0; //Start of new data transfer, so client not up to date anymore
spi_state = SPI_TRANSFER; //Change state. Ready for Tx/Rx
// printstrln("SCLK gone low");
break;
//Wait on RX buffer if we're in the transfer state
case (spi_state == SPI_TRANSFER) => p_spi.mosi :> >> in_data_rev: //notice extra >> which rotates byte to MSB
// if (buff_index == 0){
// out_data_rev = 0xAA; //Calculate next tx byte to send
// p_spi.miso <: out_data_rev; //Load it into the port buffer
// }
// rx_ptr[spi_buf_inuse][buff_index] = (unsigned char) bitrev(in_data_rev); //pack received byte into rx array
out_data_rev = bitrev(spi_miso_buffer[spi_miso_index]) >> 24;
p_spi.miso <: out_data_rev;
if(spi_miso_index != mng_miso_index)
{
spi_miso_index++;
spi_miso_index = spi_miso_index % MISO_BUFFER_LENGTH;
}
spic <: (unsigned char) bitrev(in_data_rev);
// buff_index++; //Set index for next byte in current buffer
// if (buff_index == BUFFER_LENGTH){ //Finished tx/rx of buffer. Exit into IDLE
// spi_state = SPI_IDLE; //Ensure we're idle if SS is high (de-asserted)
//// printstrln("Buffer tx/rx complete");
// spi_buf_inuse = spi_buf_inuse ? 0 : 1; //Swap buffers by toggling index
// // i_app.transfer_notify(); //Tell client that a SPI transfer has happened
// }
break;
when I program my board and test a simple SPI communication I never see the FSM to activate the SPI_TRANSFER state.
I verified the correct sensing of spi_clk signal sensing. It seems that the miso and mosi port doesn't work on clk edges.
In the same application I have a simple blinking led thah always work well.
I cannot figure out what's the matter, because the same firmware, with only different ports used for SPI, is correctly working if downloaded on a startKit.
Could someone help me, please?
configure_in_port seems not to work
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Which 1 bit port pins are you using for SPI communication? If you are using any of the following 1 bit ports XS1_PORT_1A, XS1_PORT_1B, XS1_PORT_1C, XS1_PORT_1D and you configured your device to boot from SPI flash, this is expected. when the device is set to boot from SPI flash, !A,1B,1C and 1D are used to boot the application code in to the memory from the SPI flash device.