FPGA JTAG Chain Intergration Topic is solved
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jambun
- Member
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- Joined: Tue Jun 24, 2014 12:42 pm
FPGA JTAG Chain Intergration
Hi, Is it possible to fully integrate an XS1-A10 into the JTAG chain of an Altera FPGA device, obviously not using the two debug programs at the same time? Has anybody done this?Cheers.
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williamc1014
- Junior Member
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- Joined: Thu Apr 03, 2014 10:54 am
You may refer to the source code on https://github.com/rh387/ov2 which contains the full implementation of communication to FPGA.
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stdefeber
- Active Member
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- Joined: Wed Dec 18, 2013 9:20 pm
As far as I know every device, being an FPGA or other chip, has its own JTAG ID.
So debugging, once a chain is correctly discovered and devices acknowledged in the debugging SW, is done on ID basis.
So debugging, once a chain is correctly discovered and devices acknowledged in the debugging SW, is done on ID basis.