Can I use the 4-pin port to run the spi,we use this for communicating.
Thanks!
Running SPI with 4-pin port
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martinlian
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mon2
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When you say SPI communications - is the communication bidirectional ? Single SPI slave or more than one ?
If you are planning to ONLY output data to the SPI slave then yes, you are fine to use a 4 bit port since all of the port pins will be in the same direction (output with respect to the XMOS).
Otherwise you have a single pin that must operate in an input mode to receive data from the SPI slave:
http://en.wikipedia.org/wiki/Serial_Per ... erface_Bus
which is not possible without extra external hardware methods. Some ideas to consider if you are willing to experiment are:
a) serially shift out the data to an external shift register which will present all of the OUTPUT mode data to the SPI slave and then output enable this group of data as static. That is, the serial data should only be seen by the SPI slave after the bits are stable.
b) respectively apply an open drain (open collector) buffer on the MISO pin from the SPI SLAVE with a pull-up on the XMOS pin that will serve as the MISO pin. After you have performed the OUTPUT transaction (stored by the external shift register), then you can turn around the same 4 bit port block to INPUT so that you may read out the MISO pin value. The external latched data will be held in output by the external hardware.
The above is only a concept but in theory it should work well but you will lose on speed (due to the many transactions for setup / reading / writing) and more thought must be given to implementing QUAD SPI interfacing. Standard SPI mode use should be fine.
At this time of writing, recommending:
1 bit for serial_data to map to external shift register logic IC such as 74HC595 (to support MOSI, SPI_CLOCK, SPI_CS)
1 bit for clock to clock the external shift register logic IC
1 bit for MISO (with a local pull-up resistor of 10k - 47k) + open drain buffer (74HC07 or equivalent single gate)
1 bit to latch the data presented by the serial shift register to the external shift register (care must be taken so that when the 4 bit port is turned around, this pin does not alter the status of the latched data else you may break the SPI transaction)
Give it some thought but without external hardware do not believe it is possible to support SPI interfacing with bidirectional data flow on a 4 bit port.
If you are planning to ONLY output data to the SPI slave then yes, you are fine to use a 4 bit port since all of the port pins will be in the same direction (output with respect to the XMOS).
Otherwise you have a single pin that must operate in an input mode to receive data from the SPI slave:
http://en.wikipedia.org/wiki/Serial_Per ... erface_Bus
which is not possible without extra external hardware methods. Some ideas to consider if you are willing to experiment are:
a) serially shift out the data to an external shift register which will present all of the OUTPUT mode data to the SPI slave and then output enable this group of data as static. That is, the serial data should only be seen by the SPI slave after the bits are stable.
b) respectively apply an open drain (open collector) buffer on the MISO pin from the SPI SLAVE with a pull-up on the XMOS pin that will serve as the MISO pin. After you have performed the OUTPUT transaction (stored by the external shift register), then you can turn around the same 4 bit port block to INPUT so that you may read out the MISO pin value. The external latched data will be held in output by the external hardware.
The above is only a concept but in theory it should work well but you will lose on speed (due to the many transactions for setup / reading / writing) and more thought must be given to implementing QUAD SPI interfacing. Standard SPI mode use should be fine.
At this time of writing, recommending:
1 bit for serial_data to map to external shift register logic IC such as 74HC595 (to support MOSI, SPI_CLOCK, SPI_CS)
1 bit for clock to clock the external shift register logic IC
1 bit for MISO (with a local pull-up resistor of 10k - 47k) + open drain buffer (74HC07 or equivalent single gate)
1 bit to latch the data presented by the serial shift register to the external shift register (care must be taken so that when the 4 bit port is turned around, this pin does not alter the status of the latched data else you may break the SPI transaction)
Give it some thought but without external hardware do not believe it is possible to support SPI interfacing with bidirectional data flow on a 4 bit port.