I’m experiencing some issues with my design. I use a AD1955 DAC chip. The DAC chip makes a “pop” noise when leaving DSD mode.
I base my design out of the app_usb_aud_xk_u8_2c example code using the 2ioxsd configuration. I commented out the I2C to have the design run without the DAC original to the design. I monitor DSD MODE signal from the Xmos with a external controller also setting up my DAC registers. Monitoring the DSD MODE though is too late to mute the pop. So I need a “early” signal to engage PGA mute.
2 millisecond before the Xmos flags, coming out of DSD mode, my DAC starts to put out DC voltage. Attached file : Scope_8.jpg / Scope_9.jpg
How can I make the Xmos keep playing a DSD “silence” signal eventhough it is recieving no DSD data?
I want to mark that a change of PCM/DSD format is coming 100millisecond before the actual I2S/DSD format changes, so I have time to mute the output with my PGA later in the signal chain. I want the playback format keep going “Zero padding” around 100msec so I can handle the issues.
See attached picture DSDtoPCMxmos.jpg for graphic representation.
Suggestions for solving this issue?
"Pop" noise changing between DSD and PCM
-
Thomas1970
- Junior Member
- Posts: 5
- Joined: Wed Jul 09, 2014 7:13 pm
-
AlexAdvice
- XCore Addict
- Posts: 150
- Joined: Sun Feb 23, 2014 11:30 am
Hi,
I think you need to delay the outputs for 2ms using FIFO in XMOS firmware, but how to do this I don't know.
For DoP maybe it possible to make 2 checks of markers - one before FIFO, one after. The first will switch the control signals (Mute, DSP/PCM), and the second will actualy change the bus output (LRCLK->DSD), as now.
If you will do this, please share you solution, because I'm also want to avoid this pops in my design.
I think you need to delay the outputs for 2ms using FIFO in XMOS firmware, but how to do this I don't know.
For DoP maybe it possible to make 2 checks of markers - one before FIFO, one after. The first will switch the control signals (Mute, DSP/PCM), and the second will actualy change the bus output (LRCLK->DSD), as now.
If you will do this, please share you solution, because I'm also want to avoid this pops in my design.
-
AudioBoy
- Member++
- Posts: 19
- Joined: Fri Jun 13, 2014 1:35 pm
Hello friends,did you solved the pops at PCM-DSD-PCM transitions?
-
BMDMAN
- New User
- Posts: 3
- Joined: Thu Jul 18, 2013 3:47 pm
Pin 20 and 21 on the AD1955 assert a flag when the DSD mute pattern is detected. It takes about 22msecs to assert.
Your processor should monitor one of those. (They also asset on PCM zero too)
Brandon
Your processor should monitor one of those. (They also asset on PCM zero too)
Brandon
-
Thomas1970
- Junior Member
- Posts: 5
- Joined: Wed Jul 09, 2014 7:13 pm
Hi Brandon,
Unfortunately when the Zero flag pins rises, the DAC output has already negative saturated for 24ms. So this method will not supress the loud POP. Right now I'm doing a monitor for the DSD MODE pin from the XMOS device. This way I will be able to shorten the POP to about 2-3ms, then at least it will not be like banging a kick drum... If I was able to FiFo the DSD data, and DSD clock about 4ms and keep the DSD MODE pin operation I would be able to completely supress the issue. Are you a XMOS firmware guy? I think all my issues would be fixable inside the XMOS firmware, but I'm not a firmware guy...
Best regards,
Thomas
Unfortunately when the Zero flag pins rises, the DAC output has already negative saturated for 24ms. So this method will not supress the loud POP. Right now I'm doing a monitor for the DSD MODE pin from the XMOS device. This way I will be able to shorten the POP to about 2-3ms, then at least it will not be like banging a kick drum... If I was able to FiFo the DSD data, and DSD clock about 4ms and keep the DSD MODE pin operation I would be able to completely supress the issue. Are you a XMOS firmware guy? I think all my issues would be fixable inside the XMOS firmware, but I'm not a firmware guy...
Best regards,
Thomas