RGMII with externally generated 125 MHz Tx clock

[ozel]

With the xCORE-200 eXplorer kit, I noticed the TX_CLK is generated from the xcore sytsem frequency while the RX_CLK is comming from the external RGMII phy. Should it be possible to have the Ethernet MAC operating also with an externally generated TX_CLK (125 MHz) after some code changes?

For the current project, I need to lower the system clock to 480 Mhz to be able to gererate a 40 MHz port clock (maybe 80 MHz, if inputting still works). But then the 125 MHz cannot be derived anymore for the RGMII block within the chip.

In general, more insight on how the RGMII is achieved would be really nice. For example, the app. note could explain why certain delay values are set for certain pins etc.

[srinie]

Hi,

If not had a look earlier, this link (section 11) has more insights into the GbE RGMII Phy integration:

https://www.xmos.com/download/private/X ... t%281.4%29...

 

Yeah, more details on the default configuration and delay values would be definitely helpful.

 

[larry]

It is not possible to input a clock signal as fast as 125MHz. See datasheet parameter T(XIFMAX). Unless generated internally from the RGMII block, there is no way to supply another 125MHz clock.