Output Pins - Clock Rates are just counters?

[UtterNewbie]

I apologize in advance if this is the wrong sub-forum, but I need a sanity check to see if I am understanding the Port-spec documents correctly.

The internal hardware clockrate of an XMOS XL2xx device (REFCLKBLK = 100MHz?) is the system clock. In its most simplistic form, it is possible to toggle a pin from Logic-low to Logic-high in 1 "tick" of the REFCLKBLK (example 2.1 of XS1 Ports doc).

It looks to me that setting the basic toggle rate on that pin just manipulating the output of REFCLBLK with counters. So, to generate a timing signal of freq N on a pin, it's a matter of dividing REFCLBLK by N (Inverse PLL?). Am I reading this correctly?

Thanks,

Utter Newbie

[Ross]

Have you seen functions such as the following?

 

void configure_clock_rate(clock clk, unsigned a, unsigned b);
void configure_clock_rate_at_most(clock clk, unsigned a, unsigned b);
void configure_clock_rate_at_most(clock clk, unsigned a, unsigned b);