Thanks Seb,
Unexpected... Just to confirm, it is working, but these are unexpected transitions?
We will have a look at some stage.
Cheers,
Henk
XMOS Gigabit Ethernet TXCLK Problem
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henkVerified
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welseb
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Hey henk,henk wrote:Thanks Seb,
Unexpected... Just to confirm, it is working, but these are unexpected transitions?
We will have a look at some stage.
Cheers,
Henk
did you already check this issue?
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henkVerified
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Hi Seb,
We think that the last byte of the CRC is repeated when DV goes low.
Would you be able to confirm that in your test setup the last byte of the CRC is something like ‘0F’; or any value where the bits associated with the wires that flip on each clock cycle are different in the two nibbles of the final byte?
Cheers,
Henk
We think that the last byte of the CRC is repeated when DV goes low.
Would you be able to confirm that in your test setup the last byte of the CRC is something like ‘0F’; or any value where the bits associated with the wires that flip on each clock cycle are different in the two nibbles of the final byte?
Cheers,
Henk