High Speed data collection (DAC and ADC)

XCore Project reviews, ideas, videos and proposals.
Post Reply
User avatar
lilltroll
XCore Expert
Posts: 956
Joined: Fri Dec 11, 2009 3:53 am
Location: Sweden, Eskilstuna

High Speed data collection (DAC and ADC)

Post by lilltroll »

Status: Under development
License: Custom Licence

This projects aims to build a low-latency DAC&ADC module card to the G4 family of XMOS chips. The card will at least be able to run at 1Msample/s @ 16 bit.

The card will be equipped with a programmable signal conditioner and with programmable anti-alias filters, and a clock synthesizer. To achieve the low latency demand , SA and R-2R converters will be used - together with time-continuous anti-alias filters.


Probably not the most confused programmer anymore on the XCORE forum.
User avatar
boeserbaer
Active Member
Posts: 51
Joined: Fri Jan 29, 2010 4:36 pm

Post by boeserbaer »

Because of link compatibility issues, I am designing around the L1 series. I am almost done with a 3 core design with ethernet on 1 core, SDRAM on another, and a couple Analog Devices 16 bit 1Msps pulsar ADCs. The ADCs are configured to receive 0-5V in differentially referenced to gnd via an AD8130 diff amp. I would have preferred the G4, but my system design is around L1 links. I will post my latest schematic when it is done. It has some extra baggage from a legacy design, so there are 32 bids of digital IO also.

I suspect that for a general purpose platform, especially if using the G4 bga packages, that you would want to build a communications module with ethernet and or USB, and equip it with multiple SPI interfaces, unless the extra 1us required to read out the ADCs is crucial. By building the analog boards separately, you can use less expensive (ie 2-4 layer no bga) tech. And you could configure your analog boards for whatever inputs/outputs you desire. I would be interested in participating anyway.

mike

User avatar
shawn
XCore Addict
Posts: 238
Joined: Thu Dec 17, 2009 5:15 am

Post by shawn »

Amongst the many front~end processes the FFT is definitely a major.
I'm curious what kind of performance an Xcore can do in real-time.
If one where to need more multi~accumulates what do you think might be
a reasonable solution via cost/power. gals, fpga, sdr, forth-bots perhaps.
there are some fairly power conscientious pgpu's with in ARM. Sheeze!,
I don't know? I just keep getting that image of the robot~arm on the SAIL
computer from that movie "Demon Seed". Nickolas Wirth's Oberon runs on
ARM and is its OS, I think that it could serve and cross-compile STL C++
Binaries and hyper-visor your SYS-V, BSD, POSIX, LINUX blobages

For graphic's a Fast~Xlinked to SLI pgpu is going to have a power appetite.
The programmable abstraction likes FORTRAN good at math types. I wonder
what's new in the L2 as it relates to DSP functionality.
Is it just macros or is it in the hardware?
I'll see ; )
User avatar
shawn
XCore Addict
Posts: 238
Joined: Thu Dec 17, 2009 5:15 am

Post by shawn »

CMOS ADC's massive struts are replacing conventional exotic high-speed ADC's and because of that we all can build very fast as Tektronics or Lecroy or HP and there for bypass all that expensive IP they bundle. the savings we can poor into to class A analog to achieve optimum fidelity/$... Two of the big issues with CMOS ADC's at extreme bandwidths, are POWER and the very long data stream, because its extremely MUX'ed say 56gs/sec, with 8bit enobs each ADC will stream a packet 1kbyte wide. With an array of say XS-S's and clever multiplexing we should have an even tighter latencies than say most of the conventional scopes that utilize a bussed architecture. The power savings will come from using XMOS. And the hat trick, MIMD, should make some eyes take notice ; )...
Post Reply