I am announcing the NetStamp project
NetStamp is the opensource hardware reference implementation for the Amino project, it supports all of the basic features and requirements of that project. NetStamp provides the latest XMOS multicore technology in an accessible stamp form factor, using dual inline connectors. Now anyone can build Xmos multi core projects without the need of complex surface mount assembly and production, lowering the barrier to entry for co-creative organisations and individuals alike. But NetStamp brings much more to the party than a regular stamp, it includes 100/10 base T Ethernet networking which when used with the Amino TCP/IP stack allows construction of sophisticated Internet based devices. With this new generation of Net based stamps a whole new era of intelligent Internet devices can be envisaged, prototyped and produced at a fraction of the cost of previous solutions. NetStamp introduces event driven processing to an audience who were previously denied access due to the complexities of surface mount technology, the Amino project will achieve similar software benefits to that same audience.
Features
1. Xmos dual core XS1 L2 multiprocessing 800-1000 MIPs of event driven processing
2. Full Amino software compatibility
3. Built in Ethernet 100/10 baseT networking incl TCP/IP
4. Full Speed 480Mbits/sec USB
5. On Board Analogue I/O up to 14bit ADCs and 9 Bit DACs
6. Special function analogue blocks including, 2 capacitive sensing pins
7. Xmos Xtag/Xtag2 programming and debugging via an adaptor
8. Channel expansion to connect other Xmos devices
9. Compact size approximately 55 x 45mm
10. 4Mbits storage for amino stack and user space
11. Optional MicroSD card socket allowing Gigabytes of data and program storage
12. Total of 43 I/O lines of which 2 are dedicated I2C and 7 provide analogue functions
I will be using the first NetStamp prototypes to test and build the Amino stack over the next few months, I am looking for early adopters to join me in developing the software and hardware peripherals/daughterboards/motherboards. After the prototype build, I will perform early access build for alpha geeks and developers who would like to get onto the project early on. If your are interested and would like to reserve one of the initial dev boards please message me directly.
basic early Documentation more to come but wanted to get something up
There is still a lot of optimisation to perform on the routing and DRC, but I wanted get the basics up so you could review and give me some feedback. Let me know your thoughts.
regards
Al
NetStamp project
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NetStamp project
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Last edited by Folknology on Tue May 11, 2010 11:40 pm, edited 2 times in total.
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An even better image, Mika is working wonders with Eagle and POVRay
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Another angle showing from the network side.
PS. Yes the USB is around the wrong way, fix in process ;-)
PS. Yes the USB is around the wrong way, fix in process ;-)
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Al, great looking 3D images and a nice spec. I'm looking forward to seeing it in production.
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For those wondering about where the MicroSD card is (like Skoe), here is an underside shot - find the MicrSD holder..
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Looks really nice.Lots of features on it too.
Would be also nice to have tiny a more bare version that only has whats necessary. Just to make a xmos chip run and fit in to a breadboard.
Would be also nice to have tiny a more bare version that only has whats necessary. Just to make a xmos chip run and fit in to a breadboard.
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Thanks Berni
Don't forget Omer has a smaller L1-64 based stamp which is as you describe, I believe Leon was also working on a similar L1-64 stamp design.
NetStamp is designed to be batteries included as much as possible which is why it is larger and has more features. Eventually when the Amino software stack is in place the learning curve will also be greatly reduced for newcomers and some of the Amino features to enable that mean having a bigger board right now.
I also have some interesting breadboarding ideas, but until I get NetStamp out we won't be able to play with those concepts, watch this space, I am thinking a little differently about it...
I would also add that this is just the start, myself and others have further plans for NetStamps which include making it more compact in future, but for now we are exercising "Small steps Ellie....small steps"
regards
Al
Don't forget Omer has a smaller L1-64 based stamp which is as you describe, I believe Leon was also working on a similar L1-64 stamp design.
NetStamp is designed to be batteries included as much as possible which is why it is larger and has more features. Eventually when the Amino software stack is in place the learning curve will also be greatly reduced for newcomers and some of the Amino features to enable that mean having a bigger board right now.
I also have some interesting breadboarding ideas, but until I get NetStamp out we won't be able to play with those concepts, watch this space, I am thinking a little differently about it...
I would also add that this is just the start, myself and others have further plans for NetStamps which include making it more compact in future, but for now we are exercising "Small steps Ellie....small steps"
regards
Al
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For my one and only XMOS project, soon to be posted here, I'm in need of a NetStamp kind of board with an external RAM attached to the XMOS device. Say a mega byte or so. Whatever is remotely practical. Perhaps even SPI RAM.
What I'm talking about is my software implementation of the Zylin ZPU processor core. http://opensource.zylin.com/zpu.htm
This is a 32 bit CPU core designed for minimal usage of logic gates when implemented in an FPGA. ZyLin have provided a ZPU backend for GCC. It uses exclusively byte wide opcodes and so it is a good fit for a "virtual machine" on a micro-controller such as the XMOS executing code from external RAM with a byte wide data bus.
This is not a speed demon but a neat way to run large blobs of supervisory, management or user interface code on a micro controller with limited internal RAM.
Currently I have a ZPU in C that seems to run correctly on a my PC and a version in assembler for the Parallax Propeller chip which is almost there. I would be tempted to create an XMOS version in asm as well.
What I'm talking about is my software implementation of the Zylin ZPU processor core. http://opensource.zylin.com/zpu.htm
This is a 32 bit CPU core designed for minimal usage of logic gates when implemented in an FPGA. ZyLin have provided a ZPU backend for GCC. It uses exclusively byte wide opcodes and so it is a good fit for a "virtual machine" on a micro-controller such as the XMOS executing code from external RAM with a byte wide data bus.
This is not a speed demon but a neat way to run large blobs of supervisory, management or user interface code on a micro controller with limited internal RAM.
Currently I have a ZPU in C that seems to run correctly on a my PC and a version in assembler for the Parallax Propeller chip which is almost there. I would be tempted to create an XMOS version in asm as well.
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As I also need something like this, I wrote a PN to him this morning to see if he still works on it.Don't forget Omer has a smaller L1-64 based stamp which is as you describe
\o/ \o/ \o/ Maybe it would be possible to run it from the serial (boot) flash and use internal SRAM? Useful for code intense things like FAT32 + LFN. Should still be faster than SPIN :)What I'm talking about is my software implementation of the Zylin ZPU processor core.
@Folknology: Whoops, sorry for hijacking this thread, but I was not the first one :) I'll go on in the right thread as soon as heater released his project.
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For 1Mbyte you would a 20 bit address bus requiring 20 pins on the same port. L2 will not do this, but an L1-128 could by using its 32bit port. (Also G4 can do this of course). But even this is convoluted because the memory is treated as I/O and does not sit within the address space.
You could use SPI memory of course, but again it doesn't sit in the memory map, but if that and the delay/performance isn't a problem then its definitely possible. Using internal SRAM would of course be better but you are limited by capacity, so would have to allocate a small amount to page or cahe in from external storage. There have been some discussions around memory with XS1 and the isues are well worth reading.
You could use SPI memory of course, but again it doesn't sit in the memory map, but if that and the delay/performance isn't a problem then its definitely possible. Using internal SRAM would of course be better but you are limited by capacity, so would have to allocate a small amount to page or cahe in from external storage. There have been some discussions around memory with XS1 and the isues are well worth reading.