Code: Select all
#define BIT_TIME 34 // 340 ns versus ASIC nominal 341.3 ns
#define TIC BIT_TIME / 2
unsigned time, sync, clk = 4, dataword, k, cntr;
unsigned count64[2]; // contains 64-bit count
int inc = 6; // counter increment
int i, j, n;
timer t;
t :> time;
time += 100;
while(1) {
sync = 8;
count64[0] = 0x0; // chan 0 init
count64[1] = 0x00030000; // counts
cntr = 0x00000040U; // initial counter value
for (i=0; i<4096; i++) { // output dummy data frame
for (n=0; n<2; n++) {
k = count64[n];
for (j=0; j<16; j++) { // output 32 bit data word
dataword = sync + clk + (k & 3);
DD @ time <: dataword;
dataword = sync + (k & 3);
time += TIC; // TIC = 170, timer clock is the default 100 MHz
DD @ time <: dataword;
k = k >> 2;
sync = 0;
time += TIC;
}
}
time += TIC; //adding this additional 170 ns delay avoids the timer wrap-around
}
}
Code: Select all
DD @ time <: dataword;
Regards,
Robert Jarnot