XAI Multichannel Audio Interface

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
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lilltroll
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XAI Multichannel Audio Interface

Post by lilltroll »

Is anyone here using the XAI Multichannel Audio Interface ?

It has the low latency converters so it's intresting for me to try.
I need more analog input/output channels and more computational power compared to the L1 chip.

1) Can you connectet the XAI to the XK-XMP-64 with the 64pin IDC cable directly without any HW changes? (Is the 64pin IDC intface a "standard" XMOS interface, so any 64pin device can be connected to any other 64-pin device without problems?)

2) Can you interconnect several XC-1 or XC-2 cards over XLINK? , say 3 XC-1 and 1 XC-2 over the 5channel XLINK ?
(I already have 2 XC-1 cards, and I would like to connect them togheter and pratice before and evaluate the effects of the timedelay before I go for an XMP-64)


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lilltroll
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Post by lilltroll »

After reading the manual it seems that the XC2 card has 6 hi-speed XLINK connections available on the card while the XC1 only has 2 connections available. The USB Audio card doesn't support any links since it hasn't any XLINK pins in the XTAG2 IDC.

Would be interesting to do a X16 card with 4 G4 processors with maximum intercommunication speed.
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lilltroll
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Post by lilltroll »

Today I received a XS1-G + XAI :)
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shawn
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Post by shawn »

Today is a good day ; )
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lilltroll
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Post by lilltroll »

XMOS has updated the software examples some time ago for I2S and I2C including demo code for both USB Audio 2.0 and the XAI board. :)

Yesterday I establish I2C communication with the clock syntesizer on the XAI board. :)
But the CODEC doesn't answer my desperate calls. :cry:

I think it's time for the microscope + oscilloscope... :ugeek:

to be cont...
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lilltroll
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Post by lilltroll »

The CODEC is talking back edit: That doesn't need to be the case, since the I2C line is high by default - (but the protocol for I2C reading is not correctly defined? )

edit: The extra clock doesn't necessary mean that it's a software problem as long as the START/STOP termination is done correctly
If you read the datasheet - the "STOP"/"START" should happen without the extra clock directly. The chip address should start at clock position 19, but instead that happens at clock position 20.
Of course the CODEC will newer reply back.
XAI.png
(149.37 KiB) Not downloaded yet
XAI.png
(149.37 KiB) Not downloaded yet
(A ticket to XMOS will be created)

But why did it work for the CS2300 in the first place :?: hmmmm lets read 10Msample ....
Zooming in on a read.
CS2300.png
(54.16 KiB) Not downloaded yet
CS2300.png
(54.16 KiB) Not downloaded yet
In this case the STOP/READ happens without the extra clock.

The strange thing is that it's the same I2S code that is used in both cases.

Code: Select all

// sample second ACK.
   sda :> ack[1];
   gt :> time;
   time += 1000;
   gt when timerafter(time) :> int _;
   scl <: 0;


   // stop bit
   gt :> time;
   time += 1000 + 1000;
   gt when timerafter(time) :> int _;
   // start bit on SDI
   scl <: 1;
   sda  <: 1;
   time += 1000 + 1000;
   gt when timerafter(time) :> int _;
   scl <: 0;
   time += 1000 + 1000;
   gt when timerafter(time) :> int _;
   
   
   // send address and read
   scl <: 1;
   sda  <: 1;
   sync(sda);
   gt :> time;
   time += 1000 + 1000;
   gt when timerafter(time) :> int _;
   // start bit on SDI
   scl <: 1;
   sda  <: 0;
   gt :> time;
   time += 1000;
   gt when timerafter(time) :> int _;
   scl <: 0;
   // shift 7bits of address and 1bit R/W (fixed to write).
   // WARNING: Assume MSB first.
   for (i = 0; i < 8; i += 1) {
      int deviceAddr = device | 1;
      Temp = (deviceAddr >> (7 - i)) & 0x1;
      sda <: Temp;
      gt :> time;
      time += 1000;
      gt when timerafter(time) :> int _;
      scl <: 1;
      gt :> time;
      time += 1000;
      gt when timerafter(time) :> int _;
      scl <: 0;
   }
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lilltroll
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Post by lilltroll »

Prior the I2C, the CODEC should be held in reset, but that doesn't seem to happend.

Here comes my attempt to follow the reset pin.

In the program it's defined as:

Code: Select all

out port rst = on stdcore[1] : XS1_PORT_4C;
That maps to pin X1D14 //XMOSAudioInterface-QuickStartGuide(1v0)

That pin maps to both ULPI_DATA0, and X1E14 via an buffer //
The X1E14 is available on the left expansion port.

Nothing happens on that pin :!:

The buffers Output Enable is controlled by "XEN_ULPI_" and "XEN_LED_"
The "XEN_ULPI_" is controlled by DIPSW 6-2
The "XEN_LED_" is controlled by DIPSW 6-4

but also
"PEN_ULPI_" and "PEN_ULPI_"
controlled by DIPSW 6-1 and 6-3

DIPSW6 is not the 6:th switch in the SW-row - it seems to be connected to the "BANK3" //XMOSAudioInterface-QuickStartGuide(1v0)

But that manual assumes that the Right 64-way ICD is used (If you look at the pictures). But the software uses the Left 64-way :idea:
e.g. the "XMOSAudioInterface-QuickStartGuide" does correspond to the software examples !?

... I'm feeling the headache coming now... :x

SW6-2 = ON => Enabling the switch now generates a ~0.8s long RESET-pulse - but the amplitude of the pulse is only 0.832V high. :shock:

Someone has solder a small black wire from pin 16 on the buffer to the SD-card holder. It's some type of post-production glue there as well.

Pin 16 is output 2B2 on the buffer that seems to be forced to ground. :o
That pin is called the X1E17 which seems to be connected to the AUX_OUT CS2300 on the XAI board.

My brain now feels like this
Image
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lilltroll
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Post by lilltroll »

I rewrote the code to use the right expansion port (which is the "natural one" to use in my opinion).
Loopback streaming works and we have a liftoff. :D :D :D
I will create a project so others can access the code.
Probably not the most confused programmer anymore on the XCORE forum.
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