Interfacing both ADC and DAC to startKit to act as a digital processing unit

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Interfacing both ADC and DAC to startKit to act as a digital processing unit

Post by startKitNitwit »

Hi folks,

I have been working on a project that involves the following signal flow: PCM4202 (ADC) --------> startKit (MCU) ---------> PCM1794 (DAC)

My goal is to input a signal through the ADC then for the ADC to sample the data and output it to the control via the I2S protocol, then the controller will read it in, process it, and then output it to the DAC.

I have been trying to use the XMOS I2S library and it seems that I am either not using it right or I have a misunderstanding of what it was meant to be used for since I have a weird timing issue. Could there be a problem in the fact that both the ADC and DAC are using a 24-bit bit depth while the library (and subsequently the MCU) expects a 32-bit value as well as outputting it?

I want to rule out that I am using the library wrong before I start modifying library code so any help would be appreciated. I will try to update this thread once I go back to the lab and capture the timing behavior I have mentioned.

I have attached the code that I am using.

Some notes:
-The ADC is the master, the MCU and DAC are slaves
-The MCU is intended to act as a pass through for now, simply taking in the data and then outputting the same data
-This code was sort of frankensteined together by looking up other I2S examples and trying to get something simple to work and then build on

I am fairly new to programming on XMOS, but I am familiar with a good amount of programming so any help is appreciated. Thank you again
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Post by akp »

So long as you use the ADC and DAC in I2S or Left Justified mode and BCLK/LRCLK is 64 (i.e. 32 BCLK for left channel and 32 BCLK for right channel) then it won't matter that they use 24 bit words vs 32 bit words. It will just mean that the 8 LS bits of your input words from the ADC will be zero and the DAC will ignore the 8 LS bits of your output. You won't have to do any conversions on the data, you can operate on it just like it's 32 bit data.

I think the bigger problem is you will probably have to avoid using the ADC as I2S master if you are running it in single speed mode. According to the data sheet (p16) the BCLK/LRCLK ratio is 128 in single speed master mode, whereas the XMOS I2S slave code expects BCLK/LRCLK of 64, so of course it will never synchronize properly. If you can run the MCU as I2S master that might be a good place to start. Or you can try running the ADC in double speed or quad speed mode, in those modes it will provide BCLK/LRCLK of 64. It seems like the PCM1794 can use a BCLK/LRCLK of 128 so you could probably rewrite the I2S slave code to support BCLK/LRCLK ratio of 128 but it'll take some work and you'll get very familiar with the simulator in loopback mode.

I believe you may also have problems with your setting I2S_SLAVE_SAMPLE_ON_BCLK_FALLING unless you are 100% certain you want to do that; I would recommend the default I2S_SLAVE_SAMPLE_ON_BCLK_RISING. The PCM4202 appears to follow the standard practice of outputting on BCLK falling edge, so you would normally sample on rising edge. Likewise the PCM1794 expects its input to change on falling edge, but your setting would seem to make the input change on rising edge of BCLK.

I think your sample buffer should work OK for pass through.

Good luck.
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Post by mhelin »

So what kind of changes would be needed for the I2S library (frame-based slave) to get the 128fs bit clock of PCM4204 supported? There are no 64-bit (wide transfer) ports, so you should add an extra 32-bit read between the frames and just dump the data? Also the bclk clock definition might need some changes (MCLK/BLCK relation = 2 but sample rate is 48000 Hz where it's usually 96000 Hz).

However, I haven't check that but PCM4204 also supports TDM so that is another possible way to get data in. Might be though that TI vs. XMOS implementations differ there as well.
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Post by mhelin »

What if I just set the I2S_CHANS_PER_FRAME to 4 for I2S?