The first thing to consider is the xTAG connectivity.
The easiest thing to do is to daisy chain the xSYS connectors, using some header connectors and ribbon cable.
Note : it is important to keep the cables as short as practical.
For clarity, xSYS refers to the connectors and xTAG to the adapter.
Here is the connectivity :
xTAG TDI to TDI of board one
TDO of board one to TDI of board two
TDO of board two to xTAG TDO
xTAG TCK to TCK on both boards
xTAG TMS to TMS on both boards
The four XSYS link wires (XLUP0/1 and XLDN0/1) between the xTAG and boards one
Now you should have full xTAG and xSCOPE access
You can skip RST_N, DEBUG_N, and MSEL; they are not used for xCORE200 at present but if you want to be on the safe side gang them all up to the appropriate xTAG signals.
Pinout for the xsys connector is in the schematics : https://www.xmos.com/download/private/x ... 1.2%29.pdf
When you scan the JTAG scan chain, using xrun, you should get :
It is possible that the JTAG signals are not enjoying the extra cable length added into the scan chain so it might be necessary to slow down the JTAG as follows :
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> xrun -l Available XMOS Devices ---------------------- ID Name Adapter ID Devices -- ---- ---------- ------- 0 XMOS XTAG-3 YgYZJhvL O[0..1]
This will run the JTAG at half speed, in case this is the problem.
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> xrun --jtag-speed 1 xxx.xe
In order to build an application to run on the new 32 core network it is necessary to modify the .xn file. The attached file will provide the basic functionality.
This includes a single xCONNECT link between the boards, to start with :
The next connections to make between the boards are the xCONNECT links.
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<LinkEndpoint NodeId="0" Link="4"/> <LinkEndpoint NodeId="3" Link="4"/>
These can be used by xSCOPE, channels or interfaces.
Referring to Chapter 16 "xCORE-200 explorerKIT Portmap" in the xCORE-200 explorerKIT Hardware Manual we see that there are several options.
xCONNECT channels can operate in 2 wire or 5 wire mode. The tradeoff is that 2w mode frees up more pins for GPIO and 5w mode provides higher inter-processor bandwidth.
For this example, we will just connect Link 4 between the boards as per the .xn file entry :
Please make the following connections :
Board one : E0 in (J3 pin 32) to Board two : E0 out (J3 pin 34)
Board one : E0 out (J3 pin 34) to Board two : E0 in (J3 pin 32)
Board one : E1 out (J1 pin 24) to Board two : E1 in (J1 pin 25)
Board one : E1 in (J1 pin 25) to Board two : E1 out (J1 pin 24)
- Link 4 (also known as Link E in the xCORE-200 explorerKIT Hardware Manual) has been chosen for this example because the pins do not clash with any other functionality on the xCORE-200 explorerKITs (e.g. LEDs or buttons).
- These ports are unavailable if RGMII or USB enabled on tile 1
- Link 4 can also be used in 5 wire mode on the xCORE-200 explorerKIT, at the cost of GPIO pins
You might find the xCORE-200 Devices Portmap useful for allocating GPIO
- xCONNECT Architecture - https://www.xmos.com/download/private/x ... 1.0%29.pdf
- XS1 Link Performance and Design Guidelines - https://www.xmos.com/download/private/X ... s(2.0).pdf
- xCORE-200 explorerKIT documentation and design information (including the Portmap) : https://www.xmos.com/support/boards?product=18230
In order to booth both boards from their local FLASH you can follow this good example that uses two startkits : http://www.xcore.com/forum/viewtopic.php?f=47&t=3673