I've just been scanning the XS1-L and XS1-G documents with a view to understanding how to connect external links to other CPUs or FPGA etc. In particular I'm interested in getting the two wire links working at 5Mb/s and possibly 10Mb/s.
I have some concerns here:
Firstly the L and G links don't seem to be compatible with each other after. Apart from speed issues one has a HELLO token in its protocol the other does not. Is it possible to connect L and G devices together via their links?
From the XS1-L spec I see that the 2 wire link data rate is 160/S Mb/s where S is the switch clock speed. So 5Mb/s is easily achievable by slowing the switch clock. Alternatively the bit and token spacing can be stretched at the same switch clock speed to get down to 5Mb/s.
For the XS1-G devices the sec has a different statement of link speed. Where data rate is 320/x Mb/s where x is the bit spacing. There is no mention of switch speed. Is this correct? It seems impossible to get down to 5Mb/s by setting the bit spacing because the register for clocks between bits is only 4 bits wide. Is it possible to get a G device link down to 5Mb/s ?
In the tools manual I see how to configure the inter bit and inter token delays in xn files. Is it also possible to configure the switch clock from there?
Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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