Confusion about pins available for USB PHY for XU316-1024-QF60B-xcore_ai

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
Joe
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Post by Joe »

There isn't anything really special, perhaps this was misworded. The USB firmware uses the ports mentioned (so they are not available for application use while the USB firmware is running.

You might be able to use the same pin however if a higher precedence port is connected to it as mentioned with e.g. ports 4A and 4B.

It's probably easier to see what's possible by looking at the port map:
https://www.xmos.com/file/xcore_ai-package-port-map/

You can see the *ports* (not pins!) that become unavailable when the USB firmware is running.

Cheers,
Joe
XMOS hardware grey beard.
maxter
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Post by maxter »

Joe wrote: Wed Jun 26, 2024 4:53 pm There isn't anything really special, perhaps this was misworded. The USB firmware uses the ports mentioned (so they are not available for application use while the USB firmware is running.

You might be able to use the same pin however if a higher precedence port is connected to it as mentioned with e.g. ports 4A and 4B.

It's probably easier to see what's possible by looking at the port map:
https://www.xmos.com/file/xcore_ai-package-port-map/

You can see the *ports* (not pins!) that become unavailable when the USB firmware is running.

Cheers,
Joe
Many thanks Joe!

Now, especially after the last comment, all starts to make sense to me (I'm totally new to XMOS!), so this is the reason the QSPI module works fine on tile 0 even when the the USB_TILE is 0: because its port has precedence over the USB ones; while individual pins (1x) cannot be used because they have the highest precedence (apart from links, which I suppose would be usable).
Joe
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Post by Joe »

That's correct 😊.

USB is a slightly special case I guess as in normal use (no USB) only one of the overlapping ports has access to the IO pin (the one with highest precedence). But in the USB case the ports used for USB internally do not connect to IO pins so you can use two overlapping ports at the same time and they will both function (in this case ports 8A and 4B). 4B gets access to the pins, 8A is connected to the internal USB phy.
XMOS hardware grey beard.
maxter
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Joined: Fri Jun 14, 2024 9:55 am

Post by maxter »

Joe wrote: Thu Jun 27, 2024 12:45 pm That's correct 😊.

USB is a slightly special case I guess as in normal use (no USB) only one of the overlapping ports has access to the IO pin (the one with highest precedence). But in the USB case the ports used for USB internally do not connect to IO pins so you can use two overlapping ports at the same time and they will both function (in this case ports 8A and 4B). 4B gets access to the pins, 8A is connected to the internal USB phy.
All clear (and noted down) now, many thanks for all the clarifications.