Ethernet on XE232 Tile 3
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fabra
- Active Member
- Posts: 39
- Joined: Sat May 09, 2020 4:20 pm
Ethernet on XE232 Tile 3
I have lots of designs working with my code on XE216 and XE232. But never used Ethernet on Tile 3 before. Now is see that we are able to receive valid packets, but we are not able to send packets. Of course we analyse the RGMII timing. The hardware team is investigating that at the moment. Meanwhile I thought it was worth asking whether anyone else has done this successfully.
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infiniteimprobability
Verified - XCore Legend
- Posts: 1140
- Joined: Thu May 27, 2010 10:08 am
Hi, good to hear you have had success with gigE on xcore-200. Inside the XE232 is two identical xcore-200 silicon "nodes" (in XN speak) with the link ports connected to form a network of two "nodes", each of two tiles. The RGMII shim inside is connected to the same ports of each node in each silicon. So there is no reason why placing ethernet on a different node couldn't work. So something else must be amiss.
I am not aware of a board in XMOS on which we connected gigE to an XE232 but the silicon underneath will have been subjected to the same tests in the factory.
I am wondering if this is a tile placement issue? I had a quick look at the low level RGMII code (https://github.com/xmos/lib_ethernet/tr ... hernet/src) and didn't see any constants regarding tile placement so again, this should be OK and should work on the particular tile you choose.
What will be different on an XE232 is the channel performance "intra-tile" vs "inter-tile". Are you placing your application on a different node (i.e. EMAC on tile 2/3 and app on tile 0/1)?
Gbit Ethernet really pushes the performance of xcore-200 so slower channels might have an effect on interaction between ethernet and the app.
If the answer to the above is no, then it's time to debug and get a bit more visibility of what isn't happening, when it should. Could you use xgdb to find out where tx is getting stuck or post a state dump ( xrun --dump-state <myapp.xe>"
I am not aware of a board in XMOS on which we connected gigE to an XE232 but the silicon underneath will have been subjected to the same tests in the factory.
I am wondering if this is a tile placement issue? I had a quick look at the low level RGMII code (https://github.com/xmos/lib_ethernet/tr ... hernet/src) and didn't see any constants regarding tile placement so again, this should be OK and should work on the particular tile you choose.
What will be different on an XE232 is the channel performance "intra-tile" vs "inter-tile". Are you placing your application on a different node (i.e. EMAC on tile 2/3 and app on tile 0/1)?
Gbit Ethernet really pushes the performance of xcore-200 so slower channels might have an effect on interaction between ethernet and the app.
If the answer to the above is no, then it's time to debug and get a bit more visibility of what isn't happening, when it should. Could you use xgdb to find out where tx is getting stuck or post a state dump ( xrun --dump-state <myapp.xe>"
Engineer at XMOS