zip expense

[lukehatpadl]

Our board has two DACs which are fed by a 4 bit port. This turns out to be quite convenient as the DACs accept 64-bit words interleaved across two pins, which reduces the number of zip operations required (as the input is effectively already zipped). Four zips are required per LRCLK cycle, and are spread out as the TDM words that feed the mixer are ingested.

I'm having a bit of trouble getting the timing to work at 96k. Removing the zip instructions fixes it (but of course, no output :)). Can anyone comment on how many cycles a ZIP instruction takes?

[Joe]

zip instruction runs in a single issue slot (cycle).

[lukehatpadl]

thanks Joe! surely timing can't be that tight. I shall investigate...